Searched refs:GMAC0_DMA_TX_CTRL_ADDR (Results 1 – 2 of 2) sorted by relevance
29 #define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200) macro31 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)33 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)35 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)37 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)39 (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
63 control = readl(GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()64 writel(control | D64_XC_PD, GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()65 if (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_PD) { in dma_ctrlflags()70 writel(control, GMAC0_DMA_TX_CTRL_ADDR); in dma_ctrlflags()103 readl(GMAC0_DMA_TX_CTRL_ADDR), in dma_tx_dump()278 (readl(GMAC0_DMA_TX_CTRL_ADDR) & D64_XC_BL_MASK) in dma_init()489 writel(D64_XC_SE, GMAC0_DMA_TX_CTRL_ADDR); in gmac_disable_dma()500 writel(0, GMAC0_DMA_TX_CTRL_ADDR); in gmac_disable_dma()540 control = readl(GMAC0_DMA_TX_CTRL_ADDR); in gmac_enable_dma()546 writel(control, GMAC0_DMA_TX_CTRL_ADDR); in gmac_enable_dma()