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Searched refs:GICC_CTLR (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/irq/
H A Dirq-gic.c85 val = gicc_readl(GICC_CTLR); in int_enable_secure_signal()
87 gicc_writel(val, GICC_CTLR); in int_enable_secure_signal()
94 val = gicc_readl(GICC_CTLR); in int_disable_secure_signal()
96 gicc_writel(val, GICC_CTLR); in int_disable_secure_signal()
103 val = gicc_readl(GICC_CTLR); in int_enable_nosecure_signal()
105 gicc_writel(val, GICC_CTLR); in int_enable_nosecure_signal()
112 val = gicc_readl(GICC_CTLR); in int_disable_nosecure_signal()
114 gicc_writel(val, GICC_CTLR); in int_disable_nosecure_signal()
243 gicc_save.ctlr = gicc_readl(GICC_CTLR); in gic_irq_suspend()
296 gicc_writel(0, GICC_CTLR); in gic_irq_resume()
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/
H A Dgic.h38 #define GICC_CTLR 0x0000 macro
/OK3568_Linux_fs/u-boot/arch/arm/lib/
H A Dgic_64.S198 str w9, [x1, GICC_CTLR] /* Secure GICC_CTLR */
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/sunxi/
H A Dpsci.c306 setbits_le32(GICC_BASE + GICC_CTLR, BIT(3)); in psci_arch_init()
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S175 str r1, [r3, #GICC_CTLR] @ and clear all other bits