1*4882a593Smuzhiyun #ifndef __GIC_H__ 2*4882a593Smuzhiyun #define __GIC_H__ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun /* Register offsets for the ARM generic interrupt controller (GIC) */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #define GIC_DIST_OFFSET 0x1000 7*4882a593Smuzhiyun #define GIC_CPU_OFFSET_A9 0x0100 8*4882a593Smuzhiyun #define GIC_CPU_OFFSET_A15 0x2000 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Distributor Registers */ 11*4882a593Smuzhiyun #define GICD_CTLR 0x0000 12*4882a593Smuzhiyun #define GICD_TYPER 0x0004 13*4882a593Smuzhiyun #define GICD_IIDR 0x0008 14*4882a593Smuzhiyun #define GICD_STATUSR 0x0010 15*4882a593Smuzhiyun #define GICD_SETSPI_NSR 0x0040 16*4882a593Smuzhiyun #define GICD_CLRSPI_NSR 0x0048 17*4882a593Smuzhiyun #define GICD_SETSPI_SR 0x0050 18*4882a593Smuzhiyun #define GICD_CLRSPI_SR 0x0058 19*4882a593Smuzhiyun #define GICD_SEIR 0x0068 20*4882a593Smuzhiyun #define GICD_IGROUPRn 0x0080 21*4882a593Smuzhiyun #define GICD_ISENABLERn 0x0100 22*4882a593Smuzhiyun #define GICD_ICENABLERn 0x0180 23*4882a593Smuzhiyun #define GICD_ISPENDRn 0x0200 24*4882a593Smuzhiyun #define GICD_ICPENDRn 0x0280 25*4882a593Smuzhiyun #define GICD_ISACTIVERn 0x0300 26*4882a593Smuzhiyun #define GICD_ICACTIVERn 0x0380 27*4882a593Smuzhiyun #define GICD_IPRIORITYRn 0x0400 28*4882a593Smuzhiyun #define GICD_ITARGETSRn 0x0800 29*4882a593Smuzhiyun #define GICD_ICFGR 0x0c00 30*4882a593Smuzhiyun #define GICD_IGROUPMODRn 0x0d00 31*4882a593Smuzhiyun #define GICD_NSACRn 0x0e00 32*4882a593Smuzhiyun #define GICD_SGIR 0x0f00 33*4882a593Smuzhiyun #define GICD_CPENDSGIRn 0x0f10 34*4882a593Smuzhiyun #define GICD_SPENDSGIRn 0x0f20 35*4882a593Smuzhiyun #define GICD_IROUTERn 0x6000 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Cpu Interface Memory Mapped Registers */ 38*4882a593Smuzhiyun #define GICC_CTLR 0x0000 39*4882a593Smuzhiyun #define GICC_PMR 0x0004 40*4882a593Smuzhiyun #define GICC_BPR 0x0008 41*4882a593Smuzhiyun #define GICC_IAR 0x000C 42*4882a593Smuzhiyun #define GICC_EOIR 0x0010 43*4882a593Smuzhiyun #define GICC_RPR 0x0014 44*4882a593Smuzhiyun #define GICC_HPPIR 0x0018 45*4882a593Smuzhiyun #define GICC_ABPR 0x001c 46*4882a593Smuzhiyun #define GICC_AIAR 0x0020 47*4882a593Smuzhiyun #define GICC_AEOIR 0x0024 48*4882a593Smuzhiyun #define GICC_AHPPIR 0x0028 49*4882a593Smuzhiyun #define GICC_APRn 0x00d0 50*4882a593Smuzhiyun #define GICC_NSAPRn 0x00e0 51*4882a593Smuzhiyun #define GICC_IIDR 0x00fc 52*4882a593Smuzhiyun #define GICC_DIR 0x1000 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* ReDistributor Registers for Control and Physical LPIs */ 55*4882a593Smuzhiyun #define GICR_CTLR 0x0000 56*4882a593Smuzhiyun #define GICR_IIDR 0x0004 57*4882a593Smuzhiyun #define GICR_TYPER 0x0008 58*4882a593Smuzhiyun #define GICR_STATUSR 0x0010 59*4882a593Smuzhiyun #define GICR_WAKER 0x0014 60*4882a593Smuzhiyun #define GICR_SETLPIR 0x0040 61*4882a593Smuzhiyun #define GICR_CLRLPIR 0x0048 62*4882a593Smuzhiyun #define GICR_SEIR 0x0068 63*4882a593Smuzhiyun #define GICR_PROPBASER 0x0070 64*4882a593Smuzhiyun #define GICR_PENDBASER 0x0078 65*4882a593Smuzhiyun #define GICR_INVLPIR 0x00a0 66*4882a593Smuzhiyun #define GICR_INVALLR 0x00b0 67*4882a593Smuzhiyun #define GICR_SYNCR 0x00c0 68*4882a593Smuzhiyun #define GICR_MOVLPIR 0x0100 69*4882a593Smuzhiyun #define GICR_MOVALLR 0x0110 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* ReDistributor Registers for SGIs and PPIs */ 72*4882a593Smuzhiyun #define GICR_IGROUPRn 0x0080 73*4882a593Smuzhiyun #define GICR_ISENABLERn 0x0100 74*4882a593Smuzhiyun #define GICR_ICENABLERn 0x0180 75*4882a593Smuzhiyun #define GICR_ISPENDRn 0x0200 76*4882a593Smuzhiyun #define GICR_ICPENDRn 0x0280 77*4882a593Smuzhiyun #define GICR_ISACTIVERn 0x0300 78*4882a593Smuzhiyun #define GICR_ICACTIVERn 0x0380 79*4882a593Smuzhiyun #define GICR_IPRIORITYRn 0x0400 80*4882a593Smuzhiyun #define GICR_ICFGR0 0x0c00 81*4882a593Smuzhiyun #define GICR_ICFGR1 0x0c04 82*4882a593Smuzhiyun #define GICR_IGROUPMODRn 0x0d00 83*4882a593Smuzhiyun #define GICR_NSACRn 0x0e00 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Cpu Interface System Registers */ 86*4882a593Smuzhiyun #define ICC_IAR0_EL1 S3_0_C12_C8_0 87*4882a593Smuzhiyun #define ICC_IAR1_EL1 S3_0_C12_C12_0 88*4882a593Smuzhiyun #define ICC_EOIR0_EL1 S3_0_C12_C8_1 89*4882a593Smuzhiyun #define ICC_EOIR1_EL1 S3_0_C12_C12_1 90*4882a593Smuzhiyun #define ICC_HPPIR0_EL1 S3_0_C12_C8_2 91*4882a593Smuzhiyun #define ICC_HPPIR1_EL1 S3_0_C12_C12_2 92*4882a593Smuzhiyun #define ICC_BPR0_EL1 S3_0_C12_C8_3 93*4882a593Smuzhiyun #define ICC_BPR1_EL1 S3_0_C12_C12_3 94*4882a593Smuzhiyun #define ICC_DIR_EL1 S3_0_C12_C11_1 95*4882a593Smuzhiyun #define ICC_PMR_EL1 S3_0_C4_C6_0 96*4882a593Smuzhiyun #define ICC_RPR_EL1 S3_0_C12_C11_3 97*4882a593Smuzhiyun #define ICC_CTLR_EL1 S3_0_C12_C12_4 98*4882a593Smuzhiyun #define ICC_CTLR_EL3 S3_6_C12_C12_4 99*4882a593Smuzhiyun #define ICC_SRE_EL1 S3_0_C12_C12_5 100*4882a593Smuzhiyun #define ICC_SRE_EL2 S3_4_C12_C9_5 101*4882a593Smuzhiyun #define ICC_SRE_EL3 S3_6_C12_C12_5 102*4882a593Smuzhiyun #define ICC_IGRPEN0_EL1 S3_0_C12_C12_6 103*4882a593Smuzhiyun #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 104*4882a593Smuzhiyun #define ICC_IGRPEN1_EL3 S3_6_C12_C12_7 105*4882a593Smuzhiyun #define ICC_SEIEN_EL1 S3_0_C12_C13_0 106*4882a593Smuzhiyun #define ICC_SGI0R_EL1 S3_0_C12_C11_7 107*4882a593Smuzhiyun #define ICC_SGI1R_EL1 S3_0_C12_C11_5 108*4882a593Smuzhiyun #define ICC_ASGI1R_EL1 S3_0_C12_C11_6 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun #endif /* __GIC_H__ */ 111