Searched refs:DRAM_CLK (Results 1 – 3 of 3) sorted by relevance
20 #define DRAM_CLK (CONFIG_DRAM_CLK * 1000000) macro36 clock_set_pll5(DRAM_CLK * dram_clk_div, false); in mctl_sys_init()204 writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u); in mctl_channel_init()206 writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n); in mctl_channel_init()
25 #define DRAM_CLK (CONFIG_DRAM_CLK * 1000000) macro208 debug("Setting PLL6 to %d\n", DRAM_CLK * 2); in mctl_sys_init()209 clock_set_pll6(DRAM_CLK * 2); in mctl_sys_init()
274 config DRAM_CLK config366 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin367 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips377 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be