Searched refs:DEFAULT_MIPI_CLK_RATE (Results 1 – 1 of 1) sorted by relevance
42 #define DEFAULT_MIPI_CLK_RATE (192 * 100000L) macro228 m_n_int = lane_clock * vco_div * 1000000UL / DEFAULT_MIPI_CLK_RATE; in get_dsi_phy_ctrl()230 DEFAULT_MIPI_CLK_RATE) % in get_dsi_phy_ctrl()297 lane_clock = m_pll * (DEFAULT_MIPI_CLK_RATE / n_pll) / vco_div; in get_dsi_phy_ctrl()1223 ret = clk_set_rate(ctx->dss_dphy0_ref_clk, DEFAULT_MIPI_CLK_RATE); in dsi_parse_dt()1226 DEFAULT_MIPI_CLK_RATE, ret); in dsi_parse_dt()1230 DRM_DEBUG("dss_dphy0_ref_clk:[%lu]->[%lu].\n", DEFAULT_MIPI_CLK_RATE, in dsi_parse_dt()1239 ret = clk_set_rate(ctx->dss_dphy0_cfg_clk, DEFAULT_MIPI_CLK_RATE); in dsi_parse_dt()1243 DEFAULT_MIPI_CLK_RATE, ret); in dsi_parse_dt()1247 DRM_DEBUG("dss_dphy0_cfg_clk:[%lu]->[%lu].\n", DEFAULT_MIPI_CLK_RATE, in dsi_parse_dt()