Searched refs:DATA2 (Results 1 – 7 of 7) sorted by relevance
35 DATA2 ><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><61 DATA2 ><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><85 DATA2 ><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><__B2__><99 DATA2 ><__R2__><__G2__><__B2__><__R2__><__G2__><__B2__><__R2__><113 DATA2 ><__R2__><__G2__><__B2__><_NULL_><__R2__><__G2__><__B2__><_NULL_><
759 enum { DATA1, DATA2 }; enumerator761 #define AWE_INIT2(c) EMU8000_CMD(2,c), DATA2763 #define AWE_INIT4(c) EMU8000_CMD(3,c), DATA2
69 the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA270 to phys DATA1 and logic DATA3 to phys DATA2.
742 DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;770 DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;798 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;871 DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;911 DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
736 DATA2 = <&pio11 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;764 DATA2 = <&pio12 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;792 DATA2 = <&pio14 1 ALT2 IN SE_NICLK_IO 0 CLK_B>;865 DATA2 = <&pio12 5 ALT3 OUT SE_NICLK_IO 0 CLK_A>;905 DATA2 = <&pio11 1 ALT3 IN SE_NICLK_IO 0 CLK_A>;
218 PARTIAL_HASH--. DATA2-.
296 #define DATA2 0x24 /* Indexed register set data register */ macro