Searched refs:CQSPI_REG_CONFIG (Results 1 – 2 of 2) sorted by relevance
52 #define CQSPI_REG_CONFIG 0x00 macro162 ((readl(base + CQSPI_REG_CONFIG) >> \189 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()191 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()197 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()199 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()260 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()278 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_config_baudrate_div()288 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()296 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_set_clk_mode()[all …]
107 #define CQSPI_REG_CONFIG 0x00 macro248 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()691 reg = readl(reg_base + CQSPI_REG_CONFIG); in cqspi_chipselect()710 writel(reg, reg_base + CQSPI_REG_CONFIG); in cqspi_chipselect()765 reg = readl(reg_base + CQSPI_REG_CONFIG); in cqspi_config_baudrate_div()768 writel(reg, reg_base + CQSPI_REG_CONFIG); in cqspi_config_baudrate_div()799 reg = readl(reg_base + CQSPI_REG_CONFIG); in cqspi_controller_enable()806 writel(reg, reg_base + CQSPI_REG_CONFIG); in cqspi_controller_enable()1105 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()1107 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()