Searched refs:CPUCLK_DIV (Results 1 – 1 of 1) sorted by relevance
13 #define CPUCLK_DIV 0x24 macro59 if (readl(base + CPUCLK_DIV) & DIV_BYPASS) in tango4_clkgen_setup()65 writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */ in tango4_clkgen_setup()74 base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL); in tango4_clkgen_setup()