1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun #include <linux/kernel.h>
3*4882a593Smuzhiyun #include <linux/clk-provider.h>
4*4882a593Smuzhiyun #include <linux/of_address.h>
5*4882a593Smuzhiyun #include <linux/init.h>
6*4882a593Smuzhiyun #include <linux/io.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #define CLK_COUNT 4 /* cpu_clk, sys_clk, usb_clk, sdio_clk */
9*4882a593Smuzhiyun static struct clk *clks[CLK_COUNT];
10*4882a593Smuzhiyun static struct clk_onecell_data clk_data = { clks, CLK_COUNT };
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define SYSCLK_DIV 0x20
13*4882a593Smuzhiyun #define CPUCLK_DIV 0x24
14*4882a593Smuzhiyun #define DIV_BYPASS BIT(23)
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*** CLKGEN_PLL ***/
17*4882a593Smuzhiyun #define extract_pll_n(val) ((val >> 0) & ((1u << 7) - 1))
18*4882a593Smuzhiyun #define extract_pll_k(val) ((val >> 13) & ((1u << 3) - 1))
19*4882a593Smuzhiyun #define extract_pll_m(val) ((val >> 16) & ((1u << 3) - 1))
20*4882a593Smuzhiyun #define extract_pll_isel(val) ((val >> 24) & ((1u << 3) - 1))
21*4882a593Smuzhiyun
make_pll(int idx,const char * parent,void __iomem * base)22*4882a593Smuzhiyun static void __init make_pll(int idx, const char *parent, void __iomem *base)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun char name[8];
25*4882a593Smuzhiyun u32 val, mul, div;
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun sprintf(name, "pll%d", idx);
28*4882a593Smuzhiyun val = readl(base + idx * 8);
29*4882a593Smuzhiyun mul = extract_pll_n(val) + 1;
30*4882a593Smuzhiyun div = (extract_pll_m(val) + 1) << extract_pll_k(val);
31*4882a593Smuzhiyun clk_register_fixed_factor(NULL, name, parent, 0, mul, div);
32*4882a593Smuzhiyun if (extract_pll_isel(val) != 1)
33*4882a593Smuzhiyun panic("%s: input not set to XTAL_IN\n", name);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
make_cd(int idx,void __iomem * base)36*4882a593Smuzhiyun static void __init make_cd(int idx, void __iomem *base)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun char name[8];
39*4882a593Smuzhiyun u32 val, mul, div;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun sprintf(name, "cd%d", idx);
42*4882a593Smuzhiyun val = readl(base + idx * 8);
43*4882a593Smuzhiyun mul = 1 << 27;
44*4882a593Smuzhiyun div = (2 << 27) + val;
45*4882a593Smuzhiyun clk_register_fixed_factor(NULL, name, "pll2", 0, mul, div);
46*4882a593Smuzhiyun if (val > 0xf0000000)
47*4882a593Smuzhiyun panic("%s: unsupported divider %x\n", name, val);
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
tango4_clkgen_setup(struct device_node * np)50*4882a593Smuzhiyun static void __init tango4_clkgen_setup(struct device_node *np)
51*4882a593Smuzhiyun {
52*4882a593Smuzhiyun struct clk **pp = clk_data.clks;
53*4882a593Smuzhiyun void __iomem *base = of_iomap(np, 0);
54*4882a593Smuzhiyun const char *parent = of_clk_get_parent_name(np, 0);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (!base)
57*4882a593Smuzhiyun panic("%pOFn: invalid address\n", np);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun if (readl(base + CPUCLK_DIV) & DIV_BYPASS)
60*4882a593Smuzhiyun panic("%pOFn: unsupported cpuclk setup\n", np);
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun if (readl(base + SYSCLK_DIV) & DIV_BYPASS)
63*4882a593Smuzhiyun panic("%pOFn: unsupported sysclk setup\n", np);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun writel(0x100, base + CPUCLK_DIV); /* disable frequency ramping */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun make_pll(0, parent, base);
68*4882a593Smuzhiyun make_pll(1, parent, base);
69*4882a593Smuzhiyun make_pll(2, parent, base);
70*4882a593Smuzhiyun make_cd(2, base + 0x80);
71*4882a593Smuzhiyun make_cd(6, base + 0x80);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun pp[0] = clk_register_divider(NULL, "cpu_clk", "pll0", 0,
74*4882a593Smuzhiyun base + CPUCLK_DIV, 8, 8, CLK_DIVIDER_ONE_BASED, NULL);
75*4882a593Smuzhiyun pp[1] = clk_register_fixed_factor(NULL, "sys_clk", "pll1", 0, 1, 4);
76*4882a593Smuzhiyun pp[2] = clk_register_fixed_factor(NULL, "usb_clk", "cd2", 0, 1, 2);
77*4882a593Smuzhiyun pp[3] = clk_register_fixed_factor(NULL, "sdio_clk", "cd6", 0, 1, 2);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (IS_ERR(pp[0]) || IS_ERR(pp[1]) || IS_ERR(pp[2]) || IS_ERR(pp[3]))
80*4882a593Smuzhiyun panic("%pOFn: clk registration failed\n", np);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data))
83*4882a593Smuzhiyun panic("%pOFn: clk provider registration failed\n", np);
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun CLK_OF_DECLARE(tango4_clkgen, "sigma,tango4-clkgen", tango4_clkgen_setup);
86