Searched refs:CORE_L4_DIV (Results 1 – 2 of 2) sorted by relevance
175 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_34xx()222 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_34xx()425 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_36xx()472 clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); in dpll3_init_36xx()
26 #define CORE_L4_DIV 2 /* 83MHz : L4 */ macro