1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2006-2008 3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com> 4*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef _CLOCKS_OMAP3_H_ 9*4882a593Smuzhiyun #define _CLOCKS_OMAP3_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define PLL_STOP 1 /* PER & IVA */ 12*4882a593Smuzhiyun #define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ 13*4882a593Smuzhiyun #define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ 14*4882a593Smuzhiyun #define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * The following configurations are OPP and SysClk value independant 18*4882a593Smuzhiyun * and hence are defined here. All the other DPLL related values are 19*4882a593Smuzhiyun * tabulated in lowlevel_init.S. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* CORE DPLL */ 23*4882a593Smuzhiyun #define CORE_M3X2 2 /* 332MHz : CM_CLKSEL1_EMU */ 24*4882a593Smuzhiyun #define CORE_SSI_DIV 3 /* 221MHz : CM_CLKSEL_CORE */ 25*4882a593Smuzhiyun #define CORE_FUSB_DIV 2 /* 41.5MHz: */ 26*4882a593Smuzhiyun #define CORE_L4_DIV 2 /* 83MHz : L4 */ 27*4882a593Smuzhiyun #define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */ 28*4882a593Smuzhiyun #define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */ 29*4882a593Smuzhiyun #define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */ 30*4882a593Smuzhiyun #define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* PER DPLL */ 33*4882a593Smuzhiyun #define PER_M6X2 3 /* 288MHz: CM_CLKSEL1_EMU */ 34*4882a593Smuzhiyun #define PER_M5X2 4 /* 216MHz: CM_CLKSEL_CAM */ 35*4882a593Smuzhiyun #define PER_M4X2 2 /* 432MHz: CM_CLKSEL_DSS-dss1 */ 36*4882a593Smuzhiyun #define PER_M3X2 16 /* 54MHz : CM_CLKSEL_DSS-tv */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define CLSEL1_EMU_VAL ((CORE_M3X2 << 16) | (PER_M6X2 << 24) | (0x0A50)) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* MPU DPLL */ 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define MPU_M_12_ES1 0x0FE 43*4882a593Smuzhiyun #define MPU_N_12_ES1 0x07 44*4882a593Smuzhiyun #define MPU_FSEL_12_ES1 0x05 45*4882a593Smuzhiyun #define MPU_M2_12_ES1 0x01 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define MPU_M_12_ES2 0x0FA 48*4882a593Smuzhiyun #define MPU_N_12_ES2 0x05 49*4882a593Smuzhiyun #define MPU_FSEL_12_ES2 0x07 50*4882a593Smuzhiyun #define MPU_M2_ES2 0x01 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MPU_M_12 0x085 53*4882a593Smuzhiyun #define MPU_N_12 0x05 54*4882a593Smuzhiyun #define MPU_FSEL_12 0x07 55*4882a593Smuzhiyun #define MPU_M2_12 0x01 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define MPU_M_13_ES1 0x17D 58*4882a593Smuzhiyun #define MPU_N_13_ES1 0x0C 59*4882a593Smuzhiyun #define MPU_FSEL_13_ES1 0x03 60*4882a593Smuzhiyun #define MPU_M2_13_ES1 0x01 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #define MPU_M_13_ES2 0x258 63*4882a593Smuzhiyun #define MPU_N_13_ES2 0x0C 64*4882a593Smuzhiyun #define MPU_FSEL_13_ES2 0x03 65*4882a593Smuzhiyun #define MPU_M2_13_ES2 0x01 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define MPU_M_13 0x10A 68*4882a593Smuzhiyun #define MPU_N_13 0x0C 69*4882a593Smuzhiyun #define MPU_FSEL_13 0x03 70*4882a593Smuzhiyun #define MPU_M2_13 0x01 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define MPU_M_19P2_ES1 0x179 73*4882a593Smuzhiyun #define MPU_N_19P2_ES1 0x12 74*4882a593Smuzhiyun #define MPU_FSEL_19P2_ES1 0x04 75*4882a593Smuzhiyun #define MPU_M2_19P2_ES1 0x01 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #define MPU_M_19P2_ES2 0x271 78*4882a593Smuzhiyun #define MPU_N_19P2_ES2 0x17 79*4882a593Smuzhiyun #define MPU_FSEL_19P2_ES2 0x03 80*4882a593Smuzhiyun #define MPU_M2_19P2_ES2 0x01 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define MPU_M_19P2 0x14C 83*4882a593Smuzhiyun #define MPU_N_19P2 0x17 84*4882a593Smuzhiyun #define MPU_FSEL_19P2 0x03 85*4882a593Smuzhiyun #define MPU_M2_19P2 0x01 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define MPU_M_26_ES1 0x17D 88*4882a593Smuzhiyun #define MPU_N_26_ES1 0x19 89*4882a593Smuzhiyun #define MPU_FSEL_26_ES1 0x03 90*4882a593Smuzhiyun #define MPU_M2_26_ES1 0x01 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define MPU_M_26_ES2 0x0FA 93*4882a593Smuzhiyun #define MPU_N_26_ES2 0x0C 94*4882a593Smuzhiyun #define MPU_FSEL_26_ES2 0x07 95*4882a593Smuzhiyun #define MPU_M2_26_ES2 0x01 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define MPU_M_26 0x085 98*4882a593Smuzhiyun #define MPU_N_26 0x0C 99*4882a593Smuzhiyun #define MPU_FSEL_26 0x07 100*4882a593Smuzhiyun #define MPU_M2_26 0x01 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #define MPU_M_38P4_ES1 0x1FA 103*4882a593Smuzhiyun #define MPU_N_38P4_ES1 0x32 104*4882a593Smuzhiyun #define MPU_FSEL_38P4_ES1 0x03 105*4882a593Smuzhiyun #define MPU_M2_38P4_ES1 0x01 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun #define MPU_M_38P4_ES2 0x271 108*4882a593Smuzhiyun #define MPU_N_38P4_ES2 0x2F 109*4882a593Smuzhiyun #define MPU_FSEL_38P4_ES2 0x03 110*4882a593Smuzhiyun #define MPU_M2_38P4_ES2 0x01 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #define MPU_M_38P4 0x14C 113*4882a593Smuzhiyun #define MPU_N_38P4 0x2F 114*4882a593Smuzhiyun #define MPU_FSEL_38P4 0x03 115*4882a593Smuzhiyun #define MPU_M2_38P4 0x01 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* IVA DPLL */ 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define IVA_M_12_ES1 0x07D 120*4882a593Smuzhiyun #define IVA_N_12_ES1 0x05 121*4882a593Smuzhiyun #define IVA_FSEL_12_ES1 0x07 122*4882a593Smuzhiyun #define IVA_M2_12_ES1 0x01 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #define IVA_M_12_ES2 0x0B4 125*4882a593Smuzhiyun #define IVA_N_12_ES2 0x05 126*4882a593Smuzhiyun #define IVA_FSEL_12_ES2 0x07 127*4882a593Smuzhiyun #define IVA_M2_12_ES2 0x01 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define IVA_M_12 0x085 130*4882a593Smuzhiyun #define IVA_N_12 0x05 131*4882a593Smuzhiyun #define IVA_FSEL_12 0x07 132*4882a593Smuzhiyun #define IVA_M2_12 0x01 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define IVA_M_13_ES1 0x0FA 135*4882a593Smuzhiyun #define IVA_N_13_ES1 0x0C 136*4882a593Smuzhiyun #define IVA_FSEL_13_ES1 0x03 137*4882a593Smuzhiyun #define IVA_M2_13_ES1 0x01 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define IVA_M_13_ES2 0x168 140*4882a593Smuzhiyun #define IVA_N_13_ES2 0x0C 141*4882a593Smuzhiyun #define IVA_FSEL_13_ES2 0x03 142*4882a593Smuzhiyun #define IVA_M2_13_ES2 0x01 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define IVA_M_13 0x10A 145*4882a593Smuzhiyun #define IVA_N_13 0x0C 146*4882a593Smuzhiyun #define IVA_FSEL_13 0x03 147*4882a593Smuzhiyun #define IVA_M2_13 0x01 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun #define IVA_M_19P2_ES1 0x082 150*4882a593Smuzhiyun #define IVA_N_19P2_ES1 0x09 151*4882a593Smuzhiyun #define IVA_FSEL_19P2_ES1 0x07 152*4882a593Smuzhiyun #define IVA_M2_19P2_ES1 0x01 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define IVA_M_19P2_ES2 0x0E1 155*4882a593Smuzhiyun #define IVA_N_19P2_ES2 0x0B 156*4882a593Smuzhiyun #define IVA_FSEL_19P2_ES2 0x06 157*4882a593Smuzhiyun #define IVA_M2_19P2_ES2 0x01 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define IVA_M_19P2 0x14C 160*4882a593Smuzhiyun #define IVA_N_19P2 0x17 161*4882a593Smuzhiyun #define IVA_FSEL_19P2 0x03 162*4882a593Smuzhiyun #define IVA_M2_19P2 0x01 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define IVA_M_26_ES1 0x07D 165*4882a593Smuzhiyun #define IVA_N_26_ES1 0x0C 166*4882a593Smuzhiyun #define IVA_FSEL_26_ES1 0x07 167*4882a593Smuzhiyun #define IVA_M2_26_ES1 0x01 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define IVA_M_26_ES2 0x0B4 170*4882a593Smuzhiyun #define IVA_N_26_ES2 0x0C 171*4882a593Smuzhiyun #define IVA_FSEL_26_ES2 0x07 172*4882a593Smuzhiyun #define IVA_M2_26_ES2 0x01 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define IVA_M_26 0x085 175*4882a593Smuzhiyun #define IVA_N_26 0x0C 176*4882a593Smuzhiyun #define IVA_FSEL_26 0x07 177*4882a593Smuzhiyun #define IVA_M2_26 0x01 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun #define IVA_M_38P4_ES1 0x13F 180*4882a593Smuzhiyun #define IVA_N_38P4_ES1 0x30 181*4882a593Smuzhiyun #define IVA_FSEL_38P4_ES1 0x03 182*4882a593Smuzhiyun #define IVA_M2_38P4_ES1 0x01 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun #define IVA_M_38P4_ES2 0x0E1 185*4882a593Smuzhiyun #define IVA_N_38P4_ES2 0x17 186*4882a593Smuzhiyun #define IVA_FSEL_38P4_ES2 0x06 187*4882a593Smuzhiyun #define IVA_M2_38P4_ES2 0x01 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun #define IVA_M_38P4 0x14C 190*4882a593Smuzhiyun #define IVA_N_38P4 0x2F 191*4882a593Smuzhiyun #define IVA_FSEL_38P4 0x03 192*4882a593Smuzhiyun #define IVA_M2_38P4 0x01 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun /* CORE DPLL */ 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define CORE_M_12 0xA6 197*4882a593Smuzhiyun #define CORE_N_12 0x05 198*4882a593Smuzhiyun #define CORE_FSEL_12 0x07 199*4882a593Smuzhiyun #define CORE_M2_12 0x01 /* M3 of 2 */ 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #define CORE_M_12_ES1 0x19F 202*4882a593Smuzhiyun #define CORE_N_12_ES1 0x0E 203*4882a593Smuzhiyun #define CORE_FSL_12_ES1 0x03 204*4882a593Smuzhiyun #define CORE_M2_12_ES1 0x1 /* M3 of 2 */ 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #define CORE_M_13 0x14C 207*4882a593Smuzhiyun #define CORE_N_13 0x0C 208*4882a593Smuzhiyun #define CORE_FSEL_13 0x03 209*4882a593Smuzhiyun #define CORE_M2_13 0x01 /* M3 of 2 */ 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun #define CORE_M_13_ES1 0x1B2 212*4882a593Smuzhiyun #define CORE_N_13_ES1 0x10 213*4882a593Smuzhiyun #define CORE_FSL_13_ES1 0x03 214*4882a593Smuzhiyun #define CORE_M2_13_ES1 0x01 /* M3 of 2 */ 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun #define CORE_M_19P2 0x19F 217*4882a593Smuzhiyun #define CORE_N_19P2 0x17 218*4882a593Smuzhiyun #define CORE_FSEL_19P2 0x03 219*4882a593Smuzhiyun #define CORE_M2_19P2 0x01 /* M3 of 2 */ 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun #define CORE_M_19P2_ES1 0x19F 222*4882a593Smuzhiyun #define CORE_N_19P2_ES1 0x17 223*4882a593Smuzhiyun #define CORE_FSL_19P2_ES1 0x03 224*4882a593Smuzhiyun #define CORE_M2_19P2_ES1 0x01 /* M3 of 2 */ 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #define CORE_M_26 0xA6 227*4882a593Smuzhiyun #define CORE_N_26 0x0C 228*4882a593Smuzhiyun #define CORE_FSEL_26 0x07 229*4882a593Smuzhiyun #define CORE_M2_26 0x01 /* M3 of 2 */ 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun #define CORE_M_26_ES1 0x1B2 232*4882a593Smuzhiyun #define CORE_N_26_ES1 0x21 233*4882a593Smuzhiyun #define CORE_FSL_26_ES1 0x03 234*4882a593Smuzhiyun #define CORE_M2_26_ES1 0x01 /* M3 of 2 */ 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun #define CORE_M_38P4 0x19F 237*4882a593Smuzhiyun #define CORE_N_38P4 0x2F 238*4882a593Smuzhiyun #define CORE_FSEL_38P4 0x03 239*4882a593Smuzhiyun #define CORE_M2_38P4 0x01 /* M3 of 2 */ 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun #define CORE_M_38P4_ES1 0x19F 242*4882a593Smuzhiyun #define CORE_N_38P4_ES1 0x2F 243*4882a593Smuzhiyun #define CORE_FSL_38P4_ES1 0x03 244*4882a593Smuzhiyun #define CORE_M2_38P4_ES1 0x01 /* M3 of 2 */ 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* PER DPLL */ 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun #define PER_M_12 0xD8 249*4882a593Smuzhiyun #define PER_N_12 0x05 250*4882a593Smuzhiyun #define PER_FSEL_12 0x07 251*4882a593Smuzhiyun #define PER_M2_12 0x09 252*4882a593Smuzhiyun 253*4882a593Smuzhiyun #define PER_M_13 0x1B0 254*4882a593Smuzhiyun #define PER_N_13 0x0C 255*4882a593Smuzhiyun #define PER_FSEL_13 0x03 256*4882a593Smuzhiyun #define PER_M2_13 0x09 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun #define PER_M_19P2 0xE1 259*4882a593Smuzhiyun #define PER_N_19P2 0x09 260*4882a593Smuzhiyun #define PER_FSEL_19P2 0x07 261*4882a593Smuzhiyun #define PER_M2_19P2 0x09 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun #define PER_M_26 0xD8 264*4882a593Smuzhiyun #define PER_N_26 0x0C 265*4882a593Smuzhiyun #define PER_FSEL_26 0x07 266*4882a593Smuzhiyun #define PER_M2_26 0x09 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun #define PER_M_38P4 0xE1 269*4882a593Smuzhiyun #define PER_N_38P4 0x13 270*4882a593Smuzhiyun #define PER_FSEL_38P4 0x07 271*4882a593Smuzhiyun #define PER_M2_38P4 0x09 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun /* PER2 DPLL */ 274*4882a593Smuzhiyun #define PER2_M_12 0x78 275*4882a593Smuzhiyun #define PER2_N_12 0x0B 276*4882a593Smuzhiyun #define PER2_FSEL_12 0x03 277*4882a593Smuzhiyun #define PER2_M2_12 0x01 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun #define PER2_M_13 0x78 280*4882a593Smuzhiyun #define PER2_N_13 0x0C 281*4882a593Smuzhiyun #define PER2_FSEL_13 0x03 282*4882a593Smuzhiyun #define PER2_M2_13 0x01 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun #define PER2_M_19P2 0x2EE 285*4882a593Smuzhiyun #define PER2_N_19P2 0x0B 286*4882a593Smuzhiyun #define PER2_FSEL_19P2 0x06 287*4882a593Smuzhiyun #define PER2_M2_19P2 0x0A 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun #define PER2_M_26 0x78 290*4882a593Smuzhiyun #define PER2_N_26 0x0C 291*4882a593Smuzhiyun #define PER2_FSEL_26 0x03 292*4882a593Smuzhiyun #define PER2_M2_26 0x01 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun #define PER2_M_38P4 0x2EE 295*4882a593Smuzhiyun #define PER2_N_38P4 0x0B 296*4882a593Smuzhiyun #define PER2_FSEL_38P4 0x06 297*4882a593Smuzhiyun #define PER2_M2_38P4 0x0A 298*4882a593Smuzhiyun 299*4882a593Smuzhiyun /* 36XX PER DPLL */ 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun #define PER_36XX_M_12 0x1B0 302*4882a593Smuzhiyun #define PER_36XX_N_12 0x05 303*4882a593Smuzhiyun #define PER_36XX_FSEL_12 0x07 304*4882a593Smuzhiyun #define PER_36XX_M2_12 0x09 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun #define PER_36XX_M_13 0x360 307*4882a593Smuzhiyun #define PER_36XX_N_13 0x0C 308*4882a593Smuzhiyun #define PER_36XX_FSEL_13 0x03 309*4882a593Smuzhiyun #define PER_36XX_M2_13 0x09 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun #define PER_36XX_M_19P2 0x1C2 312*4882a593Smuzhiyun #define PER_36XX_N_19P2 0x09 313*4882a593Smuzhiyun #define PER_36XX_FSEL_19P2 0x07 314*4882a593Smuzhiyun #define PER_36XX_M2_19P2 0x09 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun #define PER_36XX_M_26 0x1B0 317*4882a593Smuzhiyun #define PER_36XX_N_26 0x0C 318*4882a593Smuzhiyun #define PER_36XX_FSEL_26 0x07 319*4882a593Smuzhiyun #define PER_36XX_M2_26 0x09 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun #define PER_36XX_M_38P4 0x1C2 322*4882a593Smuzhiyun #define PER_36XX_N_38P4 0x13 323*4882a593Smuzhiyun #define PER_36XX_FSEL_38P4 0x07 324*4882a593Smuzhiyun #define PER_36XX_M2_38P4 0x09 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun /* 36XX PER2 DPLL */ 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun #define PER2_36XX_M_12 0x50 329*4882a593Smuzhiyun #define PER2_36XX_N_12 0x00 330*4882a593Smuzhiyun #define PER2_36XX_M2_12 0x08 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun #define PER2_36XX_M_13 0x1BB 333*4882a593Smuzhiyun #define PER2_36XX_N_13 0x05 334*4882a593Smuzhiyun #define PER2_36XX_M2_13 0x08 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun #define PER2_36XX_M_19P2 0x32 337*4882a593Smuzhiyun #define PER2_36XX_N_19P2 0x00 338*4882a593Smuzhiyun #define PER2_36XX_M2_19P2 0x08 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun #define PER2_36XX_M_26 0x1BB 341*4882a593Smuzhiyun #define PER2_36XX_N_26 0x0B 342*4882a593Smuzhiyun #define PER2_36XX_M2_26 0x08 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun #define PER2_36XX_M_38P4 0x19 345*4882a593Smuzhiyun #define PER2_36XX_N_38P4 0x00 346*4882a593Smuzhiyun #define PER2_36XX_M2_38P4 0x08 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun #endif /* endif _CLOCKS_OMAP3_H_ */ 349