Searched refs:CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (Results 1 – 1 of 1) sorted by relevance
213 #define CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL (1 << 2) macro372 value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL; in pcie_phy_enable()