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Searched refs:CLK_DIV_LEFTBUS_VAL (Results 1 – 4 of 4) sorted by relevance

/OK3568_Linux_fs/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos4.c66 writel(CLK_DIV_LEFTBUS_VAL, &clk->div_leftbus); in system_clock_init()
H A Dexynos4_setup.h161 #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO)) macro
/OK3568_Linux_fs/u-boot/board/samsung/trats/
H A Dtrats.c329 writel(CLK_DIV_LEFTBUS_VAL, (unsigned int)&clk->div_leftbus); in board_clock_init()
H A Dsetup.h118 #define CLK_DIV_LEFTBUS_VAL ((GPL_RATIO << 4) | (GDL_RATIO)) macro