Searched refs:CLK_DIV_FSYS2_VAL (Results 1 – 6 of 6) sorted by relevance
70 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); in system_clock_init()
491 #define CLK_DIV_FSYS2_VAL NOT_AVAILABLE macro759 #define CLK_DIV_FSYS2_VAL 0x041d0000 macro
215 #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ macro
946 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2); in exynos5420_system_clock_init()
333 writel(CLK_DIV_FSYS2_VAL, (unsigned int)&clk->div_fsys2); in board_clock_init()
167 #define CLK_DIV_FSYS2_VAL ((MMC3_PRE_RATIO << 24) \ macro