Searched refs:CLK_DDR_PLL_SEL_SHIFT (Results 1 – 2 of 2) sorted by relevance
126 CLK_DDR_PLL_SEL_SHIFT = 8, enumerator127 CLK_DDR_PLL_SEL_MASK = 0x3 << CLK_DDR_PLL_SEL_SHIFT,
60 CLK_DDR_DIV_CON_MASK, 0 << CLK_DDR_PLL_SEL_SHIFT | in rkdclk_init()