Searched refs:BIT_DDMACH0_OWN (Results 1 – 12 of 12) sorted by relevance
759 u32 ch0_ctrl = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN); in iddma_dlfw_88xx()763 while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { in iddma_dlfw_88xx()794 while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { in iddma_en_88xx()
758 u32 ch0_ctrl = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN); in iddma_dlfw_88xx()762 while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { in iddma_dlfw_88xx()793 while (HALMAC_REG_R32(REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { in iddma_en_88xx()
509 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) in iddma_enable()518 u32 ch0_ctrl = BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN; in iddma_download_firmware()520 if (!check_hw_ready(rtwdev, REG_DDMA_CH0CTRL, BIT_DDMACH0_OWN, 0)) in iddma_download_firmware()
525 #define BIT_DDMACH0_OWN BIT(31) macro
958 u32 ch0_control = (u32)(BIT_DDMACH0_CHKSUM_EN | BIT_DDMACH0_OWN); in halmac_iddma_dlfw_88xx()966 while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { in halmac_iddma_dlfw_88xx()983 while (HALMAC_REG_READ_32(pHalmac_adapter, REG_DDMA_CH0CTRL) & BIT_DDMACH0_OWN) { in halmac_iddma_dlfw_88xx()
32788 #define BIT_DDMACH0_OWN BIT(31) macro
63828 #define BIT_DDMACH0_OWN BIT(31) macro
63829 #define BIT_DDMACH0_OWN BIT(31) macro