Searched refs:AMDGPU_UVD_FIRMWARE_OFFSET (Results 1 – 10 of 10) sorted by relevance
32 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 macro38 8) - AMDGPU_UVD_FIRMWARE_OFFSET)
417 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_mc_resume()483 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()1220 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_5_sriov_start()
242 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v3_1_mc_resume()
545 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v4_2_mc_resume()
438 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_mc_resume()494 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()1294 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v3_0_start_sriov()
262 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v5_0_mc_resume()
322 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v1_0_mc_resume_spg_mode()392 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
676 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_mc_resume()818 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in uvd_v7_0_sriov_start()
351 AMDGPU_UVD_FIRMWARE_OFFSET >> 3); in vcn_v2_0_mc_resume()419 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
593 offset = AMDGPU_UVD_FIRMWARE_OFFSET; in uvd_v6_0_mc_resume()