1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __AMDGPU_UVD_H__ 25*4882a593Smuzhiyun #define __AMDGPU_UVD_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define AMDGPU_DEFAULT_UVD_HANDLES 10 28*4882a593Smuzhiyun #define AMDGPU_MAX_UVD_HANDLES 40 29*4882a593Smuzhiyun #define AMDGPU_UVD_STACK_SIZE (200*1024) 30*4882a593Smuzhiyun #define AMDGPU_UVD_HEAP_SIZE (256*1024) 31*4882a593Smuzhiyun #define AMDGPU_UVD_SESSION_SIZE (50*1024) 32*4882a593Smuzhiyun #define AMDGPU_UVD_FIRMWARE_OFFSET 256 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AMDGPU_MAX_UVD_INSTANCES 2 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define AMDGPU_UVD_FIRMWARE_SIZE(adev) \ 37*4882a593Smuzhiyun (AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->ucode_size_bytes) + \ 38*4882a593Smuzhiyun 8) - AMDGPU_UVD_FIRMWARE_OFFSET) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct amdgpu_uvd_inst { 41*4882a593Smuzhiyun struct amdgpu_bo *vcpu_bo; 42*4882a593Smuzhiyun void *cpu_addr; 43*4882a593Smuzhiyun uint64_t gpu_addr; 44*4882a593Smuzhiyun void *saved_bo; 45*4882a593Smuzhiyun struct amdgpu_ring ring; 46*4882a593Smuzhiyun struct amdgpu_ring ring_enc[AMDGPU_MAX_UVD_ENC_RINGS]; 47*4882a593Smuzhiyun struct amdgpu_irq_src irq; 48*4882a593Smuzhiyun uint32_t srbm_soft_reset; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define AMDGPU_UVD_HARVEST_UVD0 (1 << 0) 52*4882a593Smuzhiyun #define AMDGPU_UVD_HARVEST_UVD1 (1 << 1) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct amdgpu_uvd { 55*4882a593Smuzhiyun const struct firmware *fw; /* UVD firmware */ 56*4882a593Smuzhiyun unsigned fw_version; 57*4882a593Smuzhiyun unsigned max_handles; 58*4882a593Smuzhiyun unsigned num_enc_rings; 59*4882a593Smuzhiyun uint8_t num_uvd_inst; 60*4882a593Smuzhiyun bool address_64_bit; 61*4882a593Smuzhiyun bool use_ctx_buf; 62*4882a593Smuzhiyun struct amdgpu_uvd_inst inst[AMDGPU_MAX_UVD_INSTANCES]; 63*4882a593Smuzhiyun struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 64*4882a593Smuzhiyun atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 65*4882a593Smuzhiyun struct drm_sched_entity entity; 66*4882a593Smuzhiyun struct delayed_work idle_work; 67*4882a593Smuzhiyun unsigned harvest_config; 68*4882a593Smuzhiyun /* store image width to adjust nb memory state */ 69*4882a593Smuzhiyun unsigned decode_image_width; 70*4882a593Smuzhiyun uint32_t keyselect; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun int amdgpu_uvd_sw_init(struct amdgpu_device *adev); 74*4882a593Smuzhiyun int amdgpu_uvd_sw_fini(struct amdgpu_device *adev); 75*4882a593Smuzhiyun int amdgpu_uvd_entity_init(struct amdgpu_device *adev); 76*4882a593Smuzhiyun int amdgpu_uvd_suspend(struct amdgpu_device *adev); 77*4882a593Smuzhiyun int amdgpu_uvd_resume(struct amdgpu_device *adev); 78*4882a593Smuzhiyun int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 79*4882a593Smuzhiyun struct dma_fence **fence); 80*4882a593Smuzhiyun int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 81*4882a593Smuzhiyun bool direct, struct dma_fence **fence); 82*4882a593Smuzhiyun void amdgpu_uvd_free_handles(struct amdgpu_device *adev, 83*4882a593Smuzhiyun struct drm_file *filp); 84*4882a593Smuzhiyun int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx); 85*4882a593Smuzhiyun void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring); 86*4882a593Smuzhiyun void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring); 87*4882a593Smuzhiyun int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout); 88*4882a593Smuzhiyun uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #endif 91