xref: /rk3399_ARM-atf/plat/intel/soc/common/include/socfpga_private.h (revision e85e73de43e3eb09a210cfe33fa6f00fdca5bf05)
1 /*
2  * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3  * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef SOCFPGA_PRIVATE_H
9 #define SOCFPGA_PRIVATE_H
10 
11 #include <errno.h>
12 
13 #define EMMC_DESC_SIZE		(1<<20)
14 
15 #define EMMC_INIT_PARAMS(base, clk)			\
16 	{	.bus_width = MMC_BUS_WIDTH_4,		\
17 		.clk_rate = (clk),			\
18 		.desc_base = (base),			\
19 		.desc_size = EMMC_DESC_SIZE,		\
20 		.flags = 0,				\
21 		.reg_base = SOCFPGA_MMC_REG_BASE	\
22 	}
23 
24 typedef enum {
25 	BOOT_SOURCE_FPGA = 0,
26 	BOOT_SOURCE_SDMMC,
27 	BOOT_SOURCE_NAND,
28 	BOOT_SOURCE_QSPI,
29 	BOOT_SOURCE_RSVD
30 } boot_source_type;
31 
32 /*******************************************************************************
33  * Function and variable prototypes
34  ******************************************************************************/
35 
36 void enable_nonsecure_access(void);
37 
38 void socfpga_io_setup(int boot_source, unsigned long offset);
39 
40 void socfgpa_configure_mmu_el3(unsigned long total_base,
41 			unsigned long total_size,
42 			unsigned long ro_start,
43 			unsigned long ro_limit,
44 			unsigned long coh_start,
45 			unsigned long coh_limit);
46 
47 
48 void socfpga_configure_mmu_el1(unsigned long total_base,
49 			unsigned long total_size,
50 			unsigned long ro_start,
51 			unsigned long ro_limit,
52 			unsigned long coh_start,
53 			unsigned long coh_limit);
54 
55 void socfpga_delay_timer_init(void);
56 
57 void socfpga_gic_driver_init(void);
58 
59 void socfpga_delay_timer_init_args(void);
60 
61 uint32_t socfpga_get_spsr_for_bl32_entry(void);
62 
63 uint32_t socfpga_get_spsr_for_bl33_entry(void);
64 
65 unsigned long socfpga_get_ns_image_entrypoint(void);
66 
67 void plat_secondary_cpus_bl31_entry(void);
68 
69 void setup_clusterectlr_el1(void);
70 
71 /******************************************************************************
72  * Macro for generic poling function
73  *****************************************************************************/
74 
75 #define SOCFPGA_POLL(cond, max_count, delay, delay_fn, status)	\
76 	do {							\
77 		int __count = (max_count);			\
78 		(status) = -ETIMEDOUT;				\
79 		while ((!(cond)) && (__count-- > 0)) {		\
80 			delay_fn(delay);			\
81 		}						\
82 								\
83 		if ((cond)) {					\
84 			(status) = 0;				\
85 		}						\
86 	} while (0)
87 
88 #endif /* SOCFPGA_PRIVATE_H */
89