1 /*
2 * Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
3 * Copyright (c) 2024-2025, Altera Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <errno.h>
10 #include <common/debug.h>
11 #include <drivers/delay_timer.h>
12 #include <lib/mmio.h>
13 #include <platform_def.h>
14
15 #include "socfpga_f2sdram_manager.h"
16 #include "socfpga_mailbox.h"
17 #include "socfpga_plat_def.h"
18 #include "socfpga_reset_manager.h"
19 #include "socfpga_system_manager.h"
20
deassert_peripheral_reset(void)21 void deassert_peripheral_reset(void)
22 {
23 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST),
24 RSTMGR_FIELD(PER1, WATCHDOG0) |
25 RSTMGR_FIELD(PER1, WATCHDOG1) |
26 RSTMGR_FIELD(PER1, WATCHDOG2) |
27 RSTMGR_FIELD(PER1, WATCHDOG3) |
28 RSTMGR_FIELD(PER1, WATCHDOG4) |
29 RSTMGR_FIELD(PER1, L4SYSTIMER0) |
30 RSTMGR_FIELD(PER1, L4SYSTIMER1) |
31 RSTMGR_FIELD(PER1, SPTIMER0) |
32 RSTMGR_FIELD(PER1, SPTIMER1) |
33 RSTMGR_FIELD(PER1, I2C0) |
34 RSTMGR_FIELD(PER1, I2C1) |
35 RSTMGR_FIELD(PER1, I2C2) |
36 RSTMGR_FIELD(PER1, I2C3) |
37 RSTMGR_FIELD(PER1, I2C4) |
38 RSTMGR_FIELD(PER1, I3C0) |
39 RSTMGR_FIELD(PER1, I3C1) |
40 RSTMGR_FIELD(PER1, UART0) |
41 RSTMGR_FIELD(PER1, UART1) |
42 RSTMGR_FIELD(PER1, GPIO0) |
43 RSTMGR_FIELD(PER1, GPIO1));
44
45 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
46 RSTMGR_FIELD(PER0, SOFTPHY) |
47 RSTMGR_FIELD(PER0, EMAC0OCP) |
48 RSTMGR_FIELD(PER0, EMAC1OCP) |
49 RSTMGR_FIELD(PER0, EMAC2OCP) |
50 RSTMGR_FIELD(PER0, USB0OCP) |
51 RSTMGR_FIELD(PER0, USB1OCP) |
52 RSTMGR_FIELD(PER0, NANDOCP) |
53 RSTMGR_FIELD(PER0, SDMMCOCP) |
54 RSTMGR_FIELD(PER0, DMAOCP));
55
56 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
57 RSTMGR_FIELD(PER0, EMAC0) |
58 RSTMGR_FIELD(PER0, EMAC1) |
59 RSTMGR_FIELD(PER0, EMAC2) |
60 RSTMGR_FIELD(PER0, USB0) |
61 RSTMGR_FIELD(PER0, USB1) |
62 RSTMGR_FIELD(PER0, NAND) |
63 RSTMGR_FIELD(PER0, SDMMC) |
64 RSTMGR_FIELD(PER0, DMA) |
65 RSTMGR_FIELD(PER0, SPIM0) |
66 RSTMGR_FIELD(PER0, SPIM1) |
67 RSTMGR_FIELD(PER0, SPIS0) |
68 RSTMGR_FIELD(PER0, SPIS1) |
69 RSTMGR_FIELD(PER0, EMACPTP) |
70 RSTMGR_FIELD(PER0, DMAIF0) |
71 RSTMGR_FIELD(PER0, DMAIF1) |
72 RSTMGR_FIELD(PER0, DMAIF2) |
73 RSTMGR_FIELD(PER0, DMAIF3) |
74 RSTMGR_FIELD(PER0, DMAIF4) |
75 RSTMGR_FIELD(PER0, DMAIF5) |
76 RSTMGR_FIELD(PER0, DMAIF6) |
77 RSTMGR_FIELD(PER0, DMAIF7));
78
79 #if (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || (PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5)
80 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
81 RSTMGR_FIELD(BRG, MPFE));
82 #endif
83 }
84
config_hps_hs_before_warm_reset(void)85 void config_hps_hs_before_warm_reset(void)
86 {
87 uint32_t or_mask = 0;
88
89 or_mask |= RSTMGR_HDSKEN_EMIF_FLUSH;
90 or_mask |= RSTMGR_HDSKEN_FPGAHSEN;
91 or_mask |= RSTMGR_HDSKEN_ETRSTALLEN;
92 or_mask |= RSTMGR_HDSKEN_LWS2F_FLUSH;
93 or_mask |= RSTMGR_HDSKEN_L3NOC_DBG;
94 or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC;
95
96 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask);
97 }
98
poll_idle_status(uint32_t addr,uint32_t mask,uint32_t match,uint32_t delay_ms)99 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms)
100 {
101 int time_out = delay_ms;
102
103 while (time_out-- > 0) {
104
105 if ((mmio_read_32(addr) & mask) == match) {
106 return 0;
107 }
108 udelay(1000);
109 }
110
111 return -ETIMEDOUT;
112 }
113
114 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5
poll_idle_status_by_clkcycles(uint32_t addr,uint32_t mask,uint32_t match,uint32_t delay_clk_cycles)115 static int poll_idle_status_by_clkcycles(uint32_t addr, uint32_t mask,
116 uint32_t match, uint32_t delay_clk_cycles)
117 {
118 int time_out = delay_clk_cycles;
119
120 while (time_out-- > 0) {
121
122 if ((mmio_read_32(addr) & mask) == match) {
123 return 0;
124 }
125 udelay(1);
126 }
127 return -ETIMEDOUT;
128 }
129 #endif
130
socfpga_s2f_bridge_mask(uint32_t mask,uint32_t * brg_mask,uint32_t * noc_mask)131 static void socfpga_s2f_bridge_mask(uint32_t mask,
132 uint32_t *brg_mask,
133 uint32_t *noc_mask)
134 {
135 *brg_mask = 0;
136 *noc_mask = 0;
137
138 if ((mask & SOC2FPGA_MASK) != 0U) {
139 *brg_mask |= RSTMGR_FIELD(BRG, SOC2FPGA);
140 *noc_mask |= IDLE_DATA_SOC2FPGA;
141 }
142
143 if ((mask & LWHPS2FPGA_MASK) != 0U) {
144 *brg_mask |= RSTMGR_FIELD(BRG, LWHPS2FPGA);
145 *noc_mask |= IDLE_DATA_LWSOC2FPGA;
146 }
147 }
148
socfpga_f2s_bridge_mask(uint32_t mask,uint32_t * brg_mask,uint32_t * f2s_idlereq,uint32_t * f2s_force_drain,uint32_t * f2s_en,uint32_t * f2s_idleack,uint32_t * f2s_respempty,uint32_t * f2s_cmdidle)149 static void socfpga_f2s_bridge_mask(uint32_t mask,
150 uint32_t *brg_mask,
151 uint32_t *f2s_idlereq,
152 uint32_t *f2s_force_drain,
153 uint32_t *f2s_en,
154 uint32_t *f2s_idleack,
155 uint32_t *f2s_respempty,
156 uint32_t *f2s_cmdidle)
157 {
158 *brg_mask = 0;
159 *f2s_idlereq = 0;
160 *f2s_force_drain = 0;
161 *f2s_en = 0;
162 *f2s_idleack = 0;
163 *f2s_respempty = 0;
164 *f2s_cmdidle = 0;
165
166 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
167 if ((mask & FPGA2SOC_MASK) != 0U) {
168 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
169 }
170 if ((mask & F2SDRAM0_MASK) != 0U) {
171 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0);
172 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
173 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
174 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
175 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
176 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
177 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM0_CMDIDLE;
178 }
179 if ((mask & F2SDRAM1_MASK) != 0U) {
180 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1);
181 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ;
182 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN;
183 *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE;
184 *f2s_idleack |= FLAGINSTATUS_F2SDRAM1_IDLEACK;
185 *f2s_respempty |= FLAGINSTATUS_F2SDRAM1_RESPEMPTY;
186 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM1_CMDIDLE;
187 }
188 if ((mask & F2SDRAM2_MASK) != 0U) {
189 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2);
190 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ;
191 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN;
192 *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE;
193 *f2s_idleack |= FLAGINSTATUS_F2SDRAM2_IDLEACK;
194 *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY;
195 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM2_CMDIDLE;
196 }
197 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
198 if (mask & FPGA2SOC_MASK) {
199 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
200 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
201 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
202 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
203 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
204 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
205 }
206 if (mask & F2SDRAM0_MASK) {
207 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM0);
208 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
209 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
210 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
211 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
212 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
213 }
214 if (mask & F2SDRAM1_MASK) {
215 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM1);
216 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM1_IDLEREQ;
217 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM1_FORCE_DRAIN;
218 *f2s_en |= FLAGOUTSETCLR_F2SDRAM1_ENABLE;
219 *f2s_idleack |= FLAGINSTATUS_F2SDRAM1_IDLEACK;
220 *f2s_respempty |= FLAGINSTATUS_F2SDRAM1_RESPEMPTY;
221 }
222 if (mask & F2SDRAM2_MASK) {
223 *brg_mask |= RSTMGR_FIELD(BRG, F2SSDRAM2);
224 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM2_IDLEREQ;
225 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM2_FORCE_DRAIN;
226 *f2s_en |= FLAGOUTSETCLR_F2SDRAM2_ENABLE;
227 *f2s_idleack |= FLAGINSTATUS_F2SDRAM2_IDLEACK;
228 *f2s_respempty |= FLAGINSTATUS_F2SDRAM2_RESPEMPTY;
229 }
230 #else
231 if ((mask & FPGA2SOC_MASK) != 0U) {
232 *brg_mask |= RSTMGR_FIELD(BRG, FPGA2SOC);
233 *f2s_idlereq |= FLAGOUTSETCLR_F2SDRAM0_IDLEREQ;
234 *f2s_force_drain |= FLAGOUTSETCLR_F2SDRAM0_FORCE_DRAIN;
235 *f2s_en |= FLAGOUTSETCLR_F2SDRAM0_ENABLE;
236 *f2s_idleack |= FLAGINSTATUS_F2SDRAM0_IDLEACK;
237 *f2s_respempty |= FLAGINSTATUS_F2SDRAM0_RESPEMPTY;
238 *f2s_cmdidle |= FLAGINSTATUS_F2SDRAM0_CMDIDLE;
239 }
240 #endif
241 }
242
socfpga_bridges_reset(uint32_t mask)243 int socfpga_bridges_reset(uint32_t mask)
244 {
245 int ret = 0;
246 int timeout = 300;
247 uint32_t brg_mask = 0;
248 uint32_t noc_mask = 0;
249 uint32_t f2s_idlereq = 0;
250 uint32_t f2s_force_drain = 0;
251 uint32_t f2s_en = 0;
252 uint32_t f2s_idleack = 0;
253 uint32_t f2s_respempty = 0;
254 uint32_t f2s_cmdidle = 0;
255
256 /* Reset s2f bridge */
257 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
258 if (brg_mask) {
259 if (mask & SOC2FPGA_MASK) {
260 /* Request handshake with SOC2FPGA bridge to clear traffic */
261 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
262 RSTMGR_HDSKREQ_S2F_FLUSH);
263
264 /* Wait for bridge to idle status */
265 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
266 RSTMGR_HDSKACK_S2F_FLUSH,
267 RSTMGR_HDSKACK_S2F_FLUSH, 300);
268 }
269
270 if (mask & LWHPS2FPGA_MASK) {
271 /* Request handshake with LWSOC2FPGA bridge to clear traffic */
272 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
273 RSTMGR_HDSKREQ_LWS2F_FLUSH);
274
275 /* Wait for bridge to idle status */
276 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
277 RSTMGR_HDSKACK_LWS2F_FLUSH,
278 RSTMGR_HDSKACK_LWS2F_FLUSH, 300);
279 }
280
281 if (ret < 0) {
282 ERROR("S2F Bridge reset: Timeout waiting for idle ack\n");
283 assert(false);
284 }
285
286 /* Assert reset to bridge */
287 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
288 brg_mask);
289
290 /* Clear idle requests to bridge */
291 if (mask & SOC2FPGA_MASK) {
292 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
293 RSTMGR_HDSKREQ_S2F_FLUSH);
294 }
295
296 if (mask & LWHPS2FPGA_MASK) {
297 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
298 RSTMGR_HDSKREQ_LWS2F_FLUSH);
299 }
300
301 /* When FPGA reconfig is complete */
302 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
303 }
304
305 /* Reset f2s bridge */
306 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
307 &f2s_force_drain, &f2s_en,
308 &f2s_idleack, &f2s_respempty,
309 &f2s_cmdidle);
310
311 if (brg_mask) {
312 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
313 RSTMGR_HDSKEN_FPGAHSEN);
314
315 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
316 RSTMGR_HDSKREQ_FPGAHSREQ);
317
318 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
319 RSTMGR_HDSKACK_FPGAHSREQ,
320 RSTMGR_HDSKACK_FPGAHSREQ, 300);
321
322 if (ret < 0) {
323 ERROR("F2S Bridge disable: Timeout waiting for idle req\n");
324 assert(false);
325 }
326
327 /* Disable f2s bridge */
328 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
329 f2s_en);
330 udelay(5);
331
332 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
333 f2s_force_drain);
334 udelay(5);
335
336 do {
337 /* Read response queue status to ensure it is empty */
338 uint32_t idle_status;
339
340 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(
341 SIDEBANDMGR_FLAGINSTATUS0));
342 if (idle_status & f2s_respempty) {
343 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(
344 SIDEBANDMGR_FLAGINSTATUS0));
345 if (idle_status & f2s_respempty) {
346 break;
347 }
348 }
349 udelay(1000);
350 } while (timeout-- > 0);
351
352 /* Assert reset to f2s bridge */
353 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
354 brg_mask);
355
356 /* Clear idle request to FPGA */
357 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
358 RSTMGR_HDSKREQ_FPGAHSREQ);
359
360 /* Clear idle request to MPFE */
361 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
362 f2s_idlereq);
363
364 /* When FPGA reconfig is complete */
365 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
366
367 /* Enable f2s bridge */
368 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
369 f2s_idlereq);
370
371 ret = poll_idle_status(SOCFPGA_F2SDRAMMGR(
372 SIDEBANDMGR_FLAGINSTATUS0), f2s_idleack, 0, 300);
373 if (ret < 0) {
374 ERROR("F2S bridge enable: Timeout waiting for idle ack");
375 assert(false);
376 }
377
378 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
379 f2s_force_drain);
380 udelay(5);
381
382 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
383 f2s_en);
384 udelay(5);
385 }
386
387 return ret;
388 }
389
390 /* TODO: Function too long, shall refactor */
socfpga_bridges_enable(uint32_t mask)391 int socfpga_bridges_enable(uint32_t mask)
392 {
393 int ret = 0;
394 int ret_hps = 0;
395 uint32_t brg_mask = 0;
396 uint32_t noc_mask = 0;
397 uint32_t f2s_idlereq = 0;
398 uint32_t f2s_force_drain = 0;
399 uint32_t f2s_en = 0;
400 uint32_t f2s_idleack = 0;
401 uint32_t f2s_respempty = 0;
402 uint32_t f2s_cmdidle = 0;
403 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
404 uint32_t brg_lst = 0;
405 #endif
406
407 /**************** SOC2FPGA ****************/
408
409 /* Enable s2f bridge */
410 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
411 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
412 brg_lst = mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST));
413 if ((brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA)
414 && ((brg_lst & RSTMGR_BRGMODRSTMASK_SOC2FPGA) != 0)) {
415 /*
416 * To request handshake
417 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 1
418 */
419 VERBOSE("Set S2F hdskreq ...\n");
420 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
421 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
422 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
423 | (RSTMGR_HDSKREQ_SOC2FPGAREQ));
424
425 udelay(1000);
426
427 /*
428 * To poll idle status
429 * Read Reset Manager hdskack[soc2fpga] = 1
430 */
431 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
432 & RSTMGR_BRGMODRST_SOC2FPGA) == 0x00) {
433 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
434 RSTMGR_HDSKREQ_SOC2FPGAREQ, RSTMGR_HDSKREQ_SOC2FPGAREQ,
435 300);
436 }
437
438 udelay(1000);
439
440 if (ret < 0) {
441 ERROR("S2F bridge enable: Timeout hdskack\n");
442 }
443
444 /*
445 * To assert reset
446 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
447 */
448 VERBOSE("Assert S2F ...\n");
449 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
450 (~brg_lst & 0x3) | RSTMGR_BRGMODRST_SOC2FPGA);
451
452 udelay(1000);
453
454 /*
455 * To clear idle request
456 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
457 */
458 VERBOSE("Clear S2F hdskreq ...\n");
459 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
460 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
461 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
462 | (RSTMGR_HDSKREQ_SOC2FPGAREQ));
463
464 udelay(1000);
465
466 /*
467 * To clear ack status
468 * Write Reset Manager hdskack[soc2fpga_flush_ack] = 1
469 * This bit is W1S/W1C
470 */
471 VERBOSE("Clear S2F hdskack ...\n");
472 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
473 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
474 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
475 | (RSTMGR_HDSKACK_SOC2FPGAACK));
476
477 udelay(1000);
478
479 /*
480 * To deassert reset
481 * Write Reset Manager brgmodrst[soc2fpga] = 0
482 */
483 VERBOSE("Deassert S2F ...\n");
484 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
485 (~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
486 | RSTMGR_BRGMODRST_LWHPS2FPGA))
487 | RSTMGR_BRGMODRST_SOC2FPGA);
488
489 /* Set System Manager soc bridge control register[soc2fpga_ready_latency_enable] = 1 */
490 VERBOSE("Set SOC soc2fpga_ready_latency_enable ...\n");
491 mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
492 SYSMGR_SOC_BRIDGE_CTRL_EN);
493 }
494
495 /**************** LWSOCFPGA ****************/
496
497 /* Enable LWSOC2FPGA bridge */
498 brg_lst = mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST));
499 if ((brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA)
500 && ((brg_lst & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) != 0)) {
501 /*
502 * To request handshake
503 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 1
504 */
505 VERBOSE("Set LWS2F hdskreq ...\n");
506 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
507 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
508 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
509 | (RSTMGR_HDSKREQ_LWSOC2FPGAREQ));
510
511 udelay(1000);
512
513 /*
514 * To poll idle status
515 * Read Reset Manager hdskack[lwsoc2fpga] = 1
516 */
517 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
518 & RSTMGR_BRGMODRST_LWHPS2FPGA) == 0x00) {
519 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
520 RSTMGR_HDSKREQ_LWSOC2FPGAREQ, RSTMGR_HDSKREQ_LWSOC2FPGAREQ,
521 300);
522 }
523
524 udelay(1000);
525
526 if (ret < 0) {
527 ERROR("LWS2F bridge enable: Timeout hdskack\n");
528 }
529
530 /*
531 * To assert reset
532 * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
533 */
534 VERBOSE("Assert LWS2F ...\n");
535 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
536 (~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
537 | RSTMGR_BRGMODRST_LWHPS2FPGA))
538 | RSTMGR_BRGMODRST_LWHPS2FPGA);
539
540 udelay(1000);
541
542 /*
543 * To clear idle request
544 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
545 */
546 VERBOSE("Clear LWS2F hdskreq ...\n");
547 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
548 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
549 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
550 | (RSTMGR_HDSKREQ_LWSOC2FPGAREQ));
551
552 udelay(1000);
553
554 /*
555 * To clear ack status
556 * Write Reset Manager hdskack[lwsoc2fpga_flush_ack] = 1
557 * This bit is W1S/W1C
558 */
559 VERBOSE("Clear LWS2F hdskack ...\n");
560 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
561 ((~(brg_lst) << 9) & (RSTMGR_HDSKREQ_LWSOC2FPGAREQ
562 | RSTMGR_HDSKREQ_SOC2FPGAREQ))
563 | (RSTMGR_HDSKACK_SOC2FPGAACK));
564
565 udelay(1000);
566
567 /*
568 * To deassert reset
569 * Write Reset Manager brgmodrst[lwsoc2fpga] = 0
570 */
571 VERBOSE("Deassert LWS2F ...\n");
572 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
573 ((~brg_lst & (RSTMGR_BRGMODRST_SOC2FPGA
574 | RSTMGR_BRGMODRST_LWHPS2FPGA)))
575 | RSTMGR_BRGMODRST_LWHPS2FPGA);
576
577 /* Set System Manager lwsoc bridge control register[lwsoc2fpga_ready_latency_enable] = 1 */
578 VERBOSE("Set LWSOC lwsoc2fpga_ready_latency_enable ...\n");
579 mmio_setbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
580 SYSMGR_LWSOC_BRIDGE_CTRL_EN);
581 }
582 #else
583 if (brg_mask != 0U) {
584 /* Clear idle request */
585 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR),
586 noc_mask);
587
588 /* De-assert all bridges */
589 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
590
591 /* Wait until idle ack becomes 0 */
592 ret_hps = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
593 noc_mask, 0, 1000);
594 }
595 #endif
596
597 /**************** FPGA2SOC ****************/
598
599 /* Enable f2s bridge */
600 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
601 &f2s_force_drain, &f2s_en,
602 &f2s_idleack, &f2s_respempty, &f2s_cmdidle);
603 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
604 /* Enable FPGA2SOC bridge */
605
606 if ((brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC)
607 && ((brg_lst & RSTMGR_BRGMODRSTMASK_FPGA2SOC) != 0)) {
608 /*
609 * To deassert reset
610 * Write Reset Manager brgmodrst[fpga2soc] = 0
611 */
612 VERBOSE("Deassert F2S ...\n");
613 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
614 RSTMGR_BRGMODRST_FPGA2SOC);
615
616 /*
617 * To clear handshake fpgahsack
618 * Write Reset Manager hdskreq[fpgahsack] = 1
619 */
620 VERBOSE("Clear FPGA hdskack(fpgahsack) ...\n");
621 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
622 RSTMGR_HDSKACK_FPGAHSACK);
623
624 /*
625 * To clear idle request
626 * Write Reset Manager hdskreq[fpgahsreq] = 0
627 */
628 VERBOSE("Clear FPGA hdskreq(fpgahsreq) ...\n");
629 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
630 RSTMGR_HDSKACK_FPGAHSREQ);
631
632 /*
633 * To poll idle status
634 * Read Reset Manager hdskack[fpgahsack] = 0
635 */
636 VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
637 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
638 & RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
639 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
640 RSTMGR_HDSKACK_FPGAHSACK,
641 RSTMGR_HDSKACK_FPGAHSACK_DASRT,
642 1000);
643 }
644
645 if (ret < 0) {
646 ERROR("F2S bridge fpga handshake fpgahsack: Timeout\n");
647 }
648
649 /*
650 * To clear handshake f2s_flush_ack
651 * Write Reset Manager hdskreq[f2s_flush_ack] = 1
652 */
653 VERBOSE("Clear F2S hdskack(f2s_flush_ack) ...\n");
654 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
655 RSTMGR_HDSKACK_F2S_FLUSH);
656
657 /*
658 * To clear idle request
659 * Write Reset Manager hdskreq[f2s_flush_req] = 0
660 */
661 VERBOSE("Clear F2S hdskreq(f2s_flush_req) ...\n");
662 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
663 RSTMGR_HDSKREQ_F2S_FLUSH);
664
665 /*
666 * To poll idle status
667 * Read Reset Manager hdskack[f2s_flush_ack] = 0
668 */
669 VERBOSE("Get F2SDRAM hdskack(f2s_flush_ack) ...\n");
670 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
671 & RSTMGR_BRGMODRST_FPGA2SOC) == 0x00) {
672 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
673 RSTMGR_HDSKACK_FPGA2SOCACK,
674 RSTMGR_HDSKACK_FPGA2SOCACK_DASRT,
675 1000);
676 }
677
678 if (ret < 0) {
679 ERROR("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
680 }
681
682 /* Write System Manager f2s_bridge_ctrl [f2soc_enable] = 1 */
683 VERBOSE("Deassert F2S f2soc_enable ...\n");
684 mmio_setbits_32(SOCFPGA_SYSMGR(F2S_BRIDGE_CTRL),
685 SYSMGR_F2S_BRIDGE_CTRL_EN);
686 }
687
688 /**************** FPGA2SDRAM ****************/
689
690 /* Enable FPGA2SDRAM bridge */
691 if ((brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0)
692 && ((brg_lst & RSTMGR_BRGMODRSTMASK_F2SDRAM0) != 0)) {
693 /*
694 * To request handshake
695 * Write Reset Manager hdsken[fpgahsen] = 1
696 */
697 VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
698 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
699
700 /*
701 * To request handshake
702 * Write Reset Manager hdskreq[fpgahsreq] = 1
703 */
704 VERBOSE("Set F2SDRAM hdskreq(fpgahsreq) ...\n");
705 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
706
707 /*
708 * To poll idle status
709 * Read Reset Manager hdskack[fpgahsack] = 1
710 */
711 VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
712 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
713 & RSTMGR_BRGMODRSTMASK_F2SDRAM0) == 0x00) {
714 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
715 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK,
716 300);
717 }
718
719 if (ret < 0) {
720 ERROR("F2SDRAM bridge fpga handshake fpgahsreq: Timeout\n");
721 }
722
723 /*
724 * To fence and drain traffic
725 * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
726 */
727 VERBOSE("Set F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
728 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
729 RSTMGR_HDSKREQ_F2SDRAM0REQ);
730
731 /*
732 * To poll idle status
733 * Read Reset Manager hdskack[f2sdram_flush_ack] = 1
734 */
735 VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
736 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
737 & RSTMGR_BRGMODRSTMASK_F2SDRAM0) == 0x00) {
738 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
739 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK,
740 300);
741 }
742
743 if (ret < 0) {
744 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_req: Timeout\n");
745 }
746
747 /*
748 * To clear idle request
749 * Write Reset Manager hdskreq[fpgahsreq] = 1
750 */
751 VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
752 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
753
754 /*
755 * To clear idle request
756 * Write Reset Manager hdskreq[f2sdram_flush_req] = 1
757 */
758 VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
759 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
760
761 /*
762 * To poll idle status
763 * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
764 */
765 VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
766 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
767 & RSTMGR_BRGMODRSTMASK_F2SDRAM0) == 0x00) {
768 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
769 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
770 300);
771 }
772
773 if (ret < 0) {
774 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_ack: Timeout\n");
775 }
776
777 /*
778 * To poll idle status
779 * Read Reset Manager hdskack[fpgahsack] = 0
780 */
781 VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
782 if ((mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST))
783 & RSTMGR_BRGMODRSTMASK_F2SDRAM0) == 0x00) {
784 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
785 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
786 300);
787 }
788
789 if (ret < 0) {
790 ERROR("F2SDRAM bridge fpga handshake fpgahsack: Timeout\n");
791 }
792
793 /*
794 * To assert reset
795 * Write Reset Manager brgmodrst[fpga2sdram] = 1
796 */
797 VERBOSE("Assert F2SDRAM ...\n");
798 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
799 RSTMGR_BRGMODRST_F2SSDRAM0);
800
801 udelay(1000);
802
803 /*
804 * To deassert reset
805 * Write Reset Manager brgmodrst[fpga2sdram] = 0
806 */
807 VERBOSE("Deassert F2SDRAM ...\n");
808 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
809 RSTMGR_BRGMODRST_F2SSDRAM0);
810 }
811 #else
812 if (brg_mask != 0U) {
813 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
814
815 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
816 f2s_idlereq);
817
818 ret = poll_idle_status(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0),
819 f2s_idleack, 0, 300);
820
821 if (ret < 0) {
822 ERROR("F2S bridge enable: Timeout idle ack");
823 }
824
825 /* Clear the force drain */
826 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
827 f2s_force_drain);
828 udelay(5);
829
830 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
831 f2s_en);
832 udelay(5);
833 }
834 #endif
835 ret = ret | ret_hps;
836 return ret;
837 }
838
socfpga_bridge_nongraceful_disable(uint32_t mask)839 int socfpga_bridge_nongraceful_disable(uint32_t mask)
840 {
841 int ret = 0;
842 int timeout = 1000;
843 uint32_t brg_mask = 0;
844 uint32_t f2s_idlereq = 0;
845 uint32_t f2s_force_drain = 0;
846 uint32_t f2s_en = 0;
847 uint32_t f2s_idleack = 0;
848 uint32_t f2s_respempty = 0;
849 uint32_t f2s_cmdidle = 0;
850
851 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
852 &f2s_force_drain, &f2s_en,
853 &f2s_idleack, &f2s_respempty, &f2s_cmdidle);
854
855 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
856 f2s_idlereq);
857
858 /* Time out Error - Bus is still active */
859 /* Performing a non-graceful shutdown with Force drain */
860 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTSET0),
861 f2s_force_drain);
862
863 ret = -ETIMEDOUT;
864 do {
865 /* Read response queue status to ensure it is empty */
866 uint32_t idle_status;
867
868 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0));
869 if ((idle_status & f2s_respempty) != 0U) {
870 idle_status = mmio_read_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGINSTATUS0));
871 if ((idle_status & f2s_respempty) != 0U) {
872 /* No time-out we are good! */
873 ret = 0;
874 break;
875 }
876 }
877
878 asm("nop");
879
880 } while (timeout-- > 0);
881
882 return ret;
883 }
884
socfpga_bridges_disable(uint32_t mask)885 int socfpga_bridges_disable(uint32_t mask)
886 {
887 int ret = 0;
888 uint32_t brg_mask = 0;
889 uint32_t noc_mask = 0;
890 uint32_t f2s_idlereq = 0;
891 uint32_t f2s_force_drain = 0;
892 uint32_t f2s_en = 0;
893 uint32_t f2s_idleack = 0;
894 uint32_t f2s_respempty = 0;
895 uint32_t f2s_cmdidle = 0;
896
897 /**************** SOC2FPGA ****************/
898
899 /* Disable s2f bridge */
900 socfpga_s2f_bridge_mask(mask, &brg_mask, &noc_mask);
901 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
902 /* Disable SOC2FPGA bridge */
903 if (brg_mask & RSTMGR_BRGMODRSTMASK_SOC2FPGA) {
904 /*
905 * To clear handshake
906 * Write Reset Manager hdskreq[soc2fpga_flush_req] = 0
907 */
908 VERBOSE("Set S2F hdskreq ...\n");
909 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
910 RSTMGR_HDSKREQ_SOC2FPGAREQ);
911
912 /*
913 * To poll idle status
914 * Read Reset Manager hdskack[soc2fpga] = 0
915 */
916 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
917 RSTMGR_HDSKACK_SOC2FPGAACK, RSTMGR_HDSKACK_SOC2FPGAACK_DASRT,
918 300);
919
920 if (ret < 0) {
921 ERROR("S2F bridge enable: Timeout hdskack\n");
922 }
923
924 /*
925 * To assert reset
926 * Write Reset Manager brgmodrst[soc2fpga] = 1
927 */
928 VERBOSE("Assert S2F ...\n");
929 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
930 RSTMGR_BRGMODRST_SOC2FPGA);
931
932 /* Clear System Manager soc bridge control register[soc2fpga_ready_latency_enable] = 1 */
933 VERBOSE("Clear SOC soc2fpga_ready_latency_enable ...\n");
934 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
935 SYSMGR_SOC_BRIDGE_CTRL_EN);
936
937 udelay(1000);
938 }
939
940 /**************** LWSOCFPGA ****************/
941
942 /* Disable LWSOC2FPGA bridge */
943 if (brg_mask & RSTMGR_BRGMODRSTMASK_LWHPS2FPGA) {
944 /*
945 * To clear handshake
946 * Write Reset Manager hdskreq[lwsoc2fpga_flush_req] = 0
947 */
948 VERBOSE("Set LWS2F hdskreq ...\n");
949 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
950 RSTMGR_HDSKREQ_LWSOC2FPGAREQ);
951
952 /*
953 * To poll idle status
954 * Read Reset Manager hdskack[lwsoc2fpga] = 0
955 */
956 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
957 RSTMGR_HDSKACK_LWSOC2FPGAACK, RSTMGR_HDSKACK_LWSOC2FPGAACK_DASRT,
958 300);
959
960 if (ret < 0) {
961 ERROR("LWS2F bridge enable: Timeout hdskack\n");
962 }
963
964 /*
965 * To assert reset
966 * Write Reset Manager brgmodrst[lwsoc2fpga] = 1
967 */
968 VERBOSE("Assert LWS2F ...\n");
969 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
970 RSTMGR_BRGMODRST_LWHPS2FPGA);
971
972 /* Clear System Manager lwsoc bridge control register[lwsoc2fpga_ready_latency_enable] = 1 */
973 VERBOSE("Clear LWSOC lwsoc2fpga_ready_latency_enable ...\n");
974 mmio_clrbits_32(SOCFPGA_SYSMGR(FPGA_BRIDGE_CTRL),
975 SYSMGR_LWSOC_BRIDGE_CTRL_EN);
976
977 udelay(1000);
978 }
979 #else
980 if (brg_mask != 0U) {
981 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET),
982 noc_mask);
983
984 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
985
986 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
987 noc_mask, noc_mask, 300);
988 if (ret < 0) {
989 ERROR("S2F Bridge disable: Timeout idle ack\n");
990 }
991
992 ret = poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS),
993 noc_mask, noc_mask, 300);
994 if (ret < 0) {
995 ERROR("S2F Bridge disable: Timeout idle status\n");
996 }
997
998 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST), brg_mask);
999
1000 mmio_write_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 0);
1001 }
1002 #endif
1003
1004 /**************** FPGA2SOC ****************/
1005
1006 /* Disable f2s bridge */
1007 socfpga_f2s_bridge_mask(mask, &brg_mask, &f2s_idlereq,
1008 &f2s_force_drain, &f2s_en,
1009 &f2s_idleack, &f2s_respempty, &f2s_cmdidle);
1010 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
1011 /* Disable FPGA2SOC bridge */
1012 if (brg_mask & RSTMGR_BRGMODRSTMASK_FPGA2SOC) {
1013 /*
1014 * To request handshake
1015 * Write Reset Manager hdsken[f2soc_flush] = 1
1016 */
1017 VERBOSE("Enable FPGA hdsken(f2soc_flush) ...\n");
1018 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
1019 RSTMGR_HDSKEN_F2S_FLUSH);
1020
1021 /*
1022 * To request handshake
1023 * Write Reset Manager hdsken[fpgahsen] = 1
1024 */
1025 VERBOSE("Enable FPGA hdsken(fpgahsen) ...\n");
1026 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
1027
1028 /*
1029 * To clear handshake fpgahsack
1030 * Write Reset Manager hdskack[fpgahsack] = 1
1031 */
1032 VERBOSE("Clear FPGA hdskack(fpgahsack) ...\n");
1033 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
1034 RSTMGR_HDSKACK_FPGAHSACK);
1035
1036 /*
1037 * To set handshake request
1038 * Write Reset Manager hdskreq[fpgahsreq] = 1
1039 */
1040 VERBOSE("Set FPGA hdskreq(fpgahsreq) ...\n");
1041 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1042 RSTMGR_HDSKREQ_FPGAHSREQ);
1043
1044 /*
1045 * To poll idle status
1046 * Read Reset Manager hdskack[fpgahsack] = 1
1047 */
1048 VERBOSE("Get FPGA hdskack(fpgahsack) ...\n");
1049 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
1050 RSTMGR_HDSKACK_FPGAHSACK,
1051 RSTMGR_HDSKACK_FPGAHSACK,
1052 1000);
1053
1054 if (ret < 0) {
1055 VERBOSE("F2S bridge fpga handshake fpgahsack: Timeout\n");
1056 }
1057
1058 /*
1059 * To clear handshake f2s_flush_ack
1060 * Write Reset Manager hdskack[f2s_flush_ack] = 1
1061 */
1062 VERBOSE("Clear F2S hdskack(f2s_flush_ack) ...\n");
1063 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKACK),
1064 RSTMGR_HDSKACK_F2S_FLUSH);
1065
1066 /*
1067 * To set handshake request
1068 * Write Reset Manager hdskreq[f2s_flush_req] = 1
1069 */
1070 VERBOSE("Set FPGA hdskreq(f2s_flush_req) ...\n");
1071 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1072 RSTMGR_HDSKREQ_F2S_FLUSH);
1073
1074 /*
1075 * To poll idle status
1076 * Read Reset Manager hdskack[f2s_flush_ack] = 1
1077 */
1078 VERBOSE("Get FPGA hdskack(f2s_flush_ack) ...\n");
1079 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
1080 RSTMGR_HDSKACK_FPGA2SOCACK,
1081 RSTMGR_HDSKACK_F2S_FLUSH,
1082 1000);
1083
1084 if (ret < 0) {
1085 VERBOSE("F2S bridge fpga handshake f2s_flush_ack: Timeout\n");
1086 }
1087
1088 /*
1089 * To assert reset
1090 * Write Reset Manager brgmodrst[fpga2soc] = 1
1091 */
1092 VERBOSE("Assert F2S ...\n");
1093 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1094 RSTMGR_BRGMODRST_FPGA2SOC);
1095 }
1096
1097 /**************** FPGA2SDRAM ****************/
1098
1099 /* Disable FPGA2SDRAM bridge */
1100 if (brg_mask & RSTMGR_BRGMODRSTMASK_F2SDRAM0) {
1101 /*
1102 * To request handshake
1103 * Write Reset Manager hdsken[fpgahsen] = 1
1104 */
1105 VERBOSE("Set F2SDRAM hdsken(fpgahsen) ...\n");
1106 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), RSTMGR_HDSKEN_FPGAHSEN);
1107
1108 /*
1109 * To clear handshake request
1110 * Write Reset Manager hdskreq[fpgahsreq] = 0
1111 */
1112 VERBOSE("Clear F2SDRAM hdskreq(fpgahsreq) ...\n");
1113 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_FPGAHSREQ);
1114
1115 /*
1116 * To clear handshake request
1117 * Write Reset Manager hdskreq[f2sdram_flush_req] = 0
1118 */
1119 VERBOSE("Clear F2SDRAM hdskreq(f2sdram_flush_req) ...\n");
1120 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ), RSTMGR_HDSKREQ_F2SDRAM0REQ);
1121
1122 /*
1123 * To poll idle status
1124 * Read Reset Manager hdskack[f2sdram_flush_ack] = 0
1125 */
1126 VERBOSE("Get F2SDRAM hdskack(f2sdram_flush_ack) ...\n");
1127 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
1128 RSTMGR_HDSKACK_F2SDRAM0ACK, RSTMGR_HDSKACK_F2SDRAM0ACK_DASRT,
1129 300);
1130
1131 if (ret < 0) {
1132 ERROR("F2SDRAM bridge fpga handshake f2sdram_flush_ack: Timeout\n");
1133 }
1134
1135 /*
1136 * To poll idle status
1137 * Read Reset Manager hdskack[fpgahsack] = 0
1138 */
1139 VERBOSE("Get F2SDRAM hdskack(fpgahsack) ...\n");
1140 ret = poll_idle_status(SOCFPGA_RSTMGR(HDSKACK),
1141 RSTMGR_HDSKACK_FPGAHSACK, RSTMGR_HDSKACK_FPGAHSACK_DASRT,
1142 300);
1143
1144 if (ret < 0) {
1145 ERROR("F2SDRAM bridge fpga handshake fpgahsack: Timeout\n");
1146 }
1147
1148 /*
1149 * To assert reset
1150 * Write Reset Manager brgmodrst[fpga2sdram] = 1
1151 */
1152 VERBOSE("Assert F2SDRAM ...\n");
1153 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1154 RSTMGR_BRGMODRST_F2SSDRAM0);
1155
1156 udelay(1000);
1157
1158 /*
1159 * Assert fpga2sdram_manager_main_SidebandManager_FlagOutClr0
1160 * f2s_ready_latency_enable
1161 */
1162 VERBOSE("Assert F2SDRAM f2s_ready_latency_enable ...\n");
1163 mmio_clrbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
1164 FLAGOUTCLR0_F2SDRAM0_ENABLE);
1165 }
1166 #else
1167 if (brg_mask != 0U) {
1168
1169 if (mmio_read_32(SOCFPGA_RSTMGR(BRGMODRST)) & brg_mask) {
1170 /* Bridge cannot be reset twice */
1171 return 0;
1172 }
1173
1174 /* Starts the fence and drain traffic from F2SDRAM to MPFE */
1175 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN),
1176 RSTMGR_HDSKEN_FPGAHSEN);
1177 udelay(5);
1178 /* Ignoring FPGA ACK as it will time-out */
1179 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1180 RSTMGR_HDSKREQ_FPGAHSREQ);
1181
1182 ret = poll_idle_status_by_clkcycles(SOCFPGA_RSTMGR(HDSKACK),
1183 RSTMGR_HDSKACK_FPGAHSREQ,
1184 RSTMGR_HDSKACK_FPGAHSREQ, 1000);
1185
1186 /* DISABLE F2S Bridge */
1187 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
1188 f2s_en);
1189 udelay(5);
1190
1191 ret = socfpga_bridge_nongraceful_disable(mask);
1192
1193 /* Bridge reset */
1194 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
1195 /* Software must never write a 0x1 to FPGA2SOC_MASK bit */
1196 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1197 brg_mask & ~RSTMGR_FIELD(BRG, FPGA2SOC));
1198 #else
1199 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
1200 brg_mask);
1201 #endif
1202 /* Re-enable traffic to SDRAM*/
1203 mmio_clrbits_32(SOCFPGA_RSTMGR(HDSKREQ),
1204 RSTMGR_HDSKREQ_FPGAHSREQ);
1205
1206 mmio_setbits_32(SOCFPGA_F2SDRAMMGR(SIDEBANDMGR_FLAGOUTCLR0),
1207 f2s_idlereq);
1208
1209 udelay(5);
1210 }
1211 #endif
1212
1213 return ret;
1214 }
1215
1216 /* CPUxRESETBASELOW */
socfpga_cpu_reset_base(unsigned int cpu_id)1217 int socfpga_cpu_reset_base(unsigned int cpu_id)
1218 {
1219 int ret = 0;
1220 uint32_t entrypoint = 0;
1221
1222 ret = socfpga_cpurstrelease(cpu_id);
1223
1224 if (ret < 0) {
1225 return RSTMGR_RET_ERROR;
1226 }
1227
1228 if (ret == RSTMGR_RET_OK) {
1229
1230 switch (cpu_id) {
1231 case 0:
1232 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_0);
1233 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_0) << 24;
1234 break;
1235
1236 case 1:
1237 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_1);
1238 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_1) << 24;
1239 break;
1240
1241 case 2:
1242 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_2);
1243 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_2) << 24;
1244 break;
1245
1246 case 3:
1247 entrypoint = mmio_read_32(SOCFPGA_RSTMGR_CPUBASELOW_3);
1248 entrypoint |= mmio_read_32(SOCFPGA_RSTMGR_CPUBASEHIGH_3) << 24;
1249 break;
1250
1251 default:
1252 break;
1253 }
1254
1255 mmio_write_64(PLAT_SEC_ENTRY, entrypoint);
1256 }
1257
1258 return RSTMGR_RET_OK;
1259 }
1260
1261 /* CPURSTRELEASE */
socfpga_cpurstrelease(unsigned int cpu_id)1262 int socfpga_cpurstrelease(unsigned int cpu_id)
1263 {
1264 unsigned int timeout = 0;
1265
1266 do {
1267 /* Read response queue status to ensure it is empty */
1268 uint32_t cpurstrelease_status;
1269
1270 cpurstrelease_status = mmio_read_32(SOCFPGA_RSTMGR(CPURSTRELEASE));
1271
1272 if ((cpurstrelease_status & RSTMGR_CPUSTRELEASE_CPUx) == cpu_id) {
1273 return RSTMGR_RET_OK;
1274 }
1275 udelay(1000);
1276 } while (timeout-- > 0);
1277
1278 return RSTMGR_RET_ERROR;
1279 }
1280