1 /*
2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
3 * Copyright (c) 2022, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <stdbool.h>
10 #include <string.h>
11
12 #include <platform_def.h>
13
14 #include <arch.h>
15 #include <arch_helpers.h>
16 #include <arch_features.h>
17 #include <bl31/interrupt_mgmt.h>
18 #include <common/bl_common.h>
19 #include <common/debug.h>
20 #include <context.h>
21 #include <drivers/arm/gicv3.h>
22 #include <lib/cpus/cpu_ops.h>
23 #include <lib/cpus/errata.h>
24 #include <lib/el3_runtime/context_mgmt.h>
25 #include <lib/el3_runtime/cpu_data.h>
26 #include <lib/el3_runtime/pubsub_events.h>
27 #include <lib/extensions/amu.h>
28 #include <lib/extensions/brbe.h>
29 #include <lib/extensions/cpa2.h>
30 #include <lib/extensions/debug_v8p9.h>
31 #include <lib/extensions/fgt2.h>
32 #include <lib/extensions/idte3.h>
33 #include <lib/extensions/mpam.h>
34 #include <lib/extensions/pauth.h>
35 #include <lib/extensions/pmuv3.h>
36 #include <lib/extensions/sme.h>
37 #include <lib/extensions/spe.h>
38 #include <lib/extensions/sve.h>
39 #include <lib/extensions/sysreg128.h>
40 #include <lib/extensions/sys_reg_trace.h>
41 #include <lib/extensions/tcr2.h>
42 #include <lib/extensions/trbe.h>
43 #include <lib/extensions/trf.h>
44 #include <lib/utils.h>
45
46 #if ENABLE_FEAT_TWED
47 /* Make sure delay value fits within the range(0-15) */
48 CASSERT(((TWED_DELAY & ~SCR_TWEDEL_MASK) == 0U), assert_twed_delay_value_check);
49 #endif /* ENABLE_FEAT_TWED */
50
51 per_world_context_t per_world_context[CPU_CONTEXT_NUM];
52
53 static void manage_extensions_nonsecure(cpu_context_t *ctx);
54 static void manage_extensions_secure(cpu_context_t *ctx);
55
56 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)))
setup_el1_context(cpu_context_t * ctx,const struct entry_point_info * ep)57 static void setup_el1_context(cpu_context_t *ctx, const struct entry_point_info *ep)
58 {
59 u_register_t sctlr_elx, actlr_elx;
60
61 /*
62 * Initialise SCTLR_EL1 to the reset value corresponding to the target
63 * execution state setting all fields rather than relying on the hw.
64 * Some fields have architecturally UNKNOWN reset values and these are
65 * set to zero.
66 *
67 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
68 *
69 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
70 * required by PSCI specification)
71 */
72 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0UL;
73 if (GET_RW(ep->spsr) == MODE_RW_64) {
74 sctlr_elx |= SCTLR_EL1_RES1;
75 } else {
76 /*
77 * If the target execution state is AArch32 then the following
78 * fields need to be set.
79 *
80 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
81 * instructions are not trapped to EL1.
82 *
83 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
84 * instructions are not trapped to EL1.
85 *
86 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
87 * CP15DMB, CP15DSB, and CP15ISB instructions.
88 */
89 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
90 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
91 }
92
93 /*
94 * If workaround of errata 764081 for Cortex-A75 is used then set
95 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
96 */
97 if (errata_a75_764081_applies()) {
98 sctlr_elx |= SCTLR_IESB_BIT;
99 }
100
101 /* Store the initialised SCTLR_EL1 value in the cpu_context */
102 write_ctx_sctlr_el1_reg_errata(ctx, sctlr_elx);
103
104 /*
105 * Base the context ACTLR_EL1 on the current value, as it is
106 * implementation defined. The context restore process will write
107 * the value from the context to the actual register and can cause
108 * problems for processor cores that don't expect certain bits to
109 * be zero.
110 */
111 actlr_elx = read_actlr_el1();
112 write_el1_ctx_common(get_el1_sysregs_ctx(ctx), actlr_el1, actlr_elx);
113 }
114 #endif /* (IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)) */
115
116 /******************************************************************************
117 * This function performs initializations that are specific to SECURE state
118 * and updates the cpu context specified by 'ctx'.
119 *****************************************************************************/
setup_secure_context(cpu_context_t * ctx,const struct entry_point_info * ep)120 static void setup_secure_context(cpu_context_t *ctx, const struct entry_point_info *ep)
121 {
122 u_register_t scr_el3;
123 el3_state_t *state;
124
125 state = get_el3state_ctx(ctx);
126 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
127
128 #if defined(IMAGE_BL31) && !defined(SPD_spmd)
129 /*
130 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
131 * indicated by the interrupt routing model for BL31.
132 */
133 scr_el3 |= get_scr_el3_from_routing_model(SECURE);
134 #endif
135
136 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */
137 if (is_feat_mte2_supported()) {
138 scr_el3 |= SCR_ATA_BIT;
139 }
140
141 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
142
143 /*
144 * Initialize EL1 context registers unless SPMC is running
145 * at S-EL2.
146 */
147 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1
148 setup_el1_context(ctx, ep);
149 #endif
150
151 manage_extensions_secure(ctx);
152 }
153
154 #if ENABLE_RME && IMAGE_BL31
155 /******************************************************************************
156 * This function performs initializations that are specific to REALM state
157 * and updates the cpu context specified by 'ctx'.
158 *
159 * NOTE: any changes to this function must be verified by an RMMD maintainer.
160 *****************************************************************************/
setup_realm_context(cpu_context_t * ctx,const struct entry_point_info * ep)161 static void setup_realm_context(cpu_context_t *ctx, const struct entry_point_info *ep)
162 {
163 u_register_t scr_el3;
164 el3_state_t *state;
165 el2_sysregs_t *el2_ctx;
166
167 state = get_el3state_ctx(ctx);
168 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
169 el2_ctx = get_el2_sysregs_ctx(ctx);
170
171 scr_el3 |= SCR_NS_BIT | SCR_NSE_BIT;
172
173 write_el2_ctx_common(el2_ctx, spsr_el2, SPSR_EL2_REALM);
174
175 /* CSV2 version 2 and above */
176 if (is_feat_csv2_2_supported()) {
177 /* Enable access to the SCXTNUM_ELx registers. */
178 scr_el3 |= SCR_EnSCXT_BIT;
179 }
180
181 if (is_feat_sctlr2_supported()) {
182 /* Set the SCTLR2En bit in SCR_EL3 to enable access to
183 * SCTLR2_ELx registers.
184 */
185 scr_el3 |= SCR_SCTLR2En_BIT;
186 }
187
188 if (is_feat_d128_supported()) {
189 /*
190 * Set the D128En bit in SCR_EL3 to enable access to 128-bit
191 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
192 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
193 */
194 scr_el3 |= SCR_D128En_BIT;
195 }
196
197 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
198
199 if (is_feat_fgt2_supported()) {
200 fgt2_enable(ctx);
201 }
202
203 if (is_feat_debugv8p9_supported()) {
204 debugv8p9_extended_bp_wp_enable(ctx);
205 }
206
207 if (is_feat_brbe_supported()) {
208 brbe_enable(ctx);
209 }
210
211 /*
212 * Enable access to TPIDR2_EL0 if SME/SME2 is enabled for Non Secure world.
213 */
214 if (is_feat_sme_supported()) {
215 sme_enable(ctx);
216 }
217
218 if (is_feat_spe_supported()) {
219 spe_disable_realm(ctx);
220 }
221
222 if (is_feat_trbe_supported()) {
223 trbe_disable_realm(ctx);
224 }
225 }
226 #endif /* ENABLE_RME && IMAGE_BL31 */
227
228 /******************************************************************************
229 * This function performs initializations that are specific to NON-SECURE state
230 * and updates the cpu context specified by 'ctx'.
231 *****************************************************************************/
setup_ns_context(cpu_context_t * ctx,const struct entry_point_info * ep)232 static void setup_ns_context(cpu_context_t *ctx, const struct entry_point_info *ep)
233 {
234 u_register_t scr_el3;
235 el3_state_t *state;
236
237 state = get_el3state_ctx(ctx);
238 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
239
240 /* SCR_NS: Set the NS bit */
241 scr_el3 |= SCR_NS_BIT;
242
243 /* Allow access to Allocation Tags when FEAT_MTE2 is implemented and enabled. */
244 if (is_feat_mte2_supported()) {
245 scr_el3 |= SCR_ATA_BIT;
246 }
247
248 /*
249 * Pointer Authentication feature, if present, is always enabled by
250 * default for Non secure lower exception levels. We do not have an
251 * explicit flag to set it. To prevent the leakage between the worlds
252 * during world switch, we enable it only for the non-secure world.
253 *
254 * CTX_INCLUDE_PAUTH_REGS flag, is explicitly used to enable for lower
255 * exception levels of secure and realm worlds.
256 *
257 * If the Secure/realm world wants to use pointer authentication,
258 * CTX_INCLUDE_PAUTH_REGS must be explicitly set to 1, in which case
259 * it will be enabled globally for all the contexts.
260 *
261 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
262 * other than EL3
263 *
264 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
265 * than EL3
266 */
267 if (!is_ctx_pauth_supported()) {
268 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
269 }
270
271 #if HANDLE_EA_EL3_FIRST_NS
272 /* SCR_EL3.EA: Route External Abort and SError Interrupt to EL3. */
273 scr_el3 |= SCR_EA_BIT;
274 #endif
275
276 #if RAS_TRAP_NS_ERR_REC_ACCESS
277 /*
278 * SCR_EL3.TERR: Trap Error record accesses. Accesses to the RAS ERR
279 * and RAS ERX registers from EL1 and EL2(from any security state)
280 * are trapped to EL3.
281 * Set here to trap only for NS EL1/EL2
282 */
283 scr_el3 |= SCR_TERR_BIT;
284 #endif
285
286 /* CSV2 version 2 and above */
287 if (is_feat_csv2_2_supported()) {
288 /* Enable access to the SCXTNUM_ELx registers. */
289 scr_el3 |= SCR_EnSCXT_BIT;
290 }
291
292 #ifdef IMAGE_BL31
293 /*
294 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
295 * indicated by the interrupt routing model for BL31.
296 */
297 scr_el3 |= get_scr_el3_from_routing_model(NON_SECURE);
298 #endif
299
300 if (is_feat_the_supported()) {
301 /* Set the RCWMASKEn bit in SCR_EL3 to enable access to
302 * RCWMASK_EL1 and RCWSMASK_EL1 registers.
303 */
304 scr_el3 |= SCR_RCWMASKEn_BIT;
305 }
306
307 if (is_feat_sctlr2_supported()) {
308 /* Set the SCTLR2En bit in SCR_EL3 to enable access to
309 * SCTLR2_ELx registers.
310 */
311 scr_el3 |= SCR_SCTLR2En_BIT;
312 }
313
314 if (is_feat_d128_supported()) {
315 /* Set the D128En bit in SCR_EL3 to enable access to 128-bit
316 * versions of TTBR0_EL1, TTBR1_EL1, RCWMASK_EL1, RCWSMASK_EL1,
317 * PAR_EL1 and TTBR1_EL2, TTBR0_EL2 and VTTBR_EL2 registers.
318 */
319 scr_el3 |= SCR_D128En_BIT;
320 }
321
322 if (is_feat_fpmr_supported()) {
323 /* Set the EnFPM bit in SCR_EL3 to enable access to FPMR
324 * register.
325 */
326 scr_el3 |= SCR_EnFPM_BIT;
327 }
328
329 if (is_feat_aie_supported()) {
330 /* Set the AIEn bit in SCR_EL3 to enable access to (A)MAIR2
331 * system registers from NS world.
332 */
333 scr_el3 |= SCR_AIEn_BIT;
334 }
335
336 if (is_feat_pfar_supported()) {
337 /* Set the PFAREn bit in SCR_EL3 to enable access to the PFAR
338 * system registers from NS world.
339 */
340 scr_el3 |= SCR_PFAREn_BIT;
341 }
342
343 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
344
345 /* Initialize EL2 context registers */
346 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
347 if (is_feat_hcx_supported()) {
348 /*
349 * Initialize register HCRX_EL2 with its init value.
350 * As the value of HCRX_EL2 is UNKNOWN on reset, there is a
351 * chance that this can lead to unexpected behavior in lower
352 * ELs that have not been updated since the introduction of
353 * this feature if not properly initialized, especially when
354 * it comes to those bits that enable/disable traps.
355 */
356 write_el2_ctx_hcx(get_el2_sysregs_ctx(ctx), hcrx_el2,
357 HCRX_EL2_INIT_VAL);
358 }
359
360 if (is_feat_fgt_supported()) {
361 /*
362 * Initialize HFG*_EL2 registers with a default value so legacy
363 * systems unaware of FEAT_FGT do not get trapped due to their lack
364 * of initialization for this feature.
365 */
366 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgitr_el2,
367 HFGITR_EL2_INIT_VAL);
368 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgrtr_el2,
369 HFGRTR_EL2_INIT_VAL);
370 write_el2_ctx_fgt(get_el2_sysregs_ctx(ctx), hfgwtr_el2,
371 HFGWTR_EL2_INIT_VAL);
372 }
373 #else
374 /* Initialize EL1 context registers */
375 setup_el1_context(ctx, ep);
376 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
377
378 manage_extensions_nonsecure(ctx);
379 }
380
381 /*******************************************************************************
382 * The following function performs initialization of the cpu_context 'ctx'
383 * for first use that is common to all security states, and sets the
384 * initial entrypoint state as specified by the entry_point_info structure.
385 *
386 * The EE and ST attributes are used to configure the endianness and secure
387 * timer availability for the new execution context.
388 ******************************************************************************/
setup_context_common(cpu_context_t * ctx,const entry_point_info_t * ep)389 static void setup_context_common(cpu_context_t *ctx, const entry_point_info_t *ep)
390 {
391 u_register_t scr_el3;
392 u_register_t mdcr_el3;
393 el3_state_t *state;
394 gp_regs_t *gp_regs;
395
396 state = get_el3state_ctx(ctx);
397
398 /* Clear any residual register values from the context */
399 zeromem(ctx, sizeof(*ctx));
400
401 /*
402 * The lower-EL context is zeroed so that no stale values leak to a world.
403 * It is assumed that an all-zero lower-EL context is good enough for it
404 * to boot correctly. However, there are very few registers where this
405 * is not true and some values need to be recreated.
406 */
407 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
408 el2_sysregs_t *el2_ctx = get_el2_sysregs_ctx(ctx);
409
410 /*
411 * These bits are set in the gicv3 driver. Losing them (especially the
412 * SRE bit) is problematic for all worlds. Henceforth recreate them.
413 */
414 u_register_t icc_sre_el2_val = ICC_SRE_DIB_BIT | ICC_SRE_DFB_BIT |
415 ICC_SRE_EN_BIT | ICC_SRE_SRE_BIT;
416 write_el2_ctx_common(el2_ctx, icc_sre_el2, icc_sre_el2_val);
417
418 /*
419 * The actlr_el2 register can be initialized in platform's reset handler
420 * and it may contain access control bits (e.g. CLUSTERPMUEN bit).
421 */
422 write_el2_ctx_common(el2_ctx, actlr_el2, read_actlr_el2());
423 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
424
425 /* Start with a clean SCR_EL3 copy as all relevant values are set */
426 scr_el3 = SCR_RESET_VAL;
427
428 /*
429 * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
430 * EL2, EL1 and EL0 are not trapped to EL3.
431 *
432 * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
433 * EL2, EL1 and EL0 are not trapped to EL3.
434 *
435 * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
436 * both Security states and both Execution states.
437 *
438 * SCR_EL3.SIF: Set to one to disable secure instruction execution from
439 * Non-secure memory.
440 */
441 scr_el3 &= ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT);
442
443 scr_el3 |= SCR_SIF_BIT;
444
445 /*
446 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
447 * Exception level as specified by SPSR.
448 */
449 if (GET_RW(ep->spsr) == MODE_RW_64) {
450 scr_el3 |= SCR_RW_BIT;
451 }
452
453 /*
454 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
455 * Secure timer registers to EL3, from AArch64 state only, if specified
456 * by the entrypoint attributes. If SEL2 is present and enabled, the ST
457 * bit always behaves as 1 (i.e. secure physical timer register access
458 * is not trapped)
459 */
460 if (EP_GET_ST(ep->h.attr) != 0U) {
461 scr_el3 |= SCR_ST_BIT;
462 }
463
464 /*
465 * If FEAT_HCX is enabled, enable access to HCRX_EL2 by setting
466 * SCR_EL3.HXEn.
467 */
468 if (is_feat_hcx_supported()) {
469 scr_el3 |= SCR_HXEn_BIT;
470 }
471
472 /*
473 * If FEAT_LS64_ACCDATA is enabled, enable access to ACCDATA_EL1 by
474 * setting SCR_EL3.ADEn and allow the ST64BV0 instruction by setting
475 * SCR_EL3.EnAS0.
476 */
477 if (is_feat_ls64_accdata_supported()) {
478 scr_el3 |= SCR_ADEn_BIT | SCR_EnAS0_BIT;
479 }
480
481 /*
482 * If FEAT_RNG_TRAP is enabled, all reads of the RNDR and RNDRRS
483 * registers are trapped to EL3.
484 */
485 if (is_feat_rng_trap_supported()) {
486 scr_el3 |= SCR_TRNDR_BIT;
487 }
488
489 #if FAULT_INJECTION_SUPPORT
490 /* Enable fault injection from lower ELs */
491 scr_el3 |= SCR_FIEN_BIT;
492 #endif
493
494 /*
495 * Enable Pointer Authentication globally for all the worlds.
496 *
497 * SCR_EL3.API: Set to one to not trap any PAuth instructions at ELs
498 * other than EL3
499 *
500 * SCR_EL3.APK: Set to one to not trap any PAuth key values at ELs other
501 * than EL3
502 */
503 if (is_ctx_pauth_supported()) {
504 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
505 }
506
507 /*
508 * SCR_EL3.PIEN: Enable permission indirection and overlay
509 * registers for AArch64 if present.
510 */
511 if (is_feat_sxpie_supported() || is_feat_sxpoe_supported()) {
512 scr_el3 |= SCR_PIEN_BIT;
513 }
514
515 /*
516 * SCR_EL3.GCSEn: Enable GCS registers for AArch64 if present.
517 */
518 if ((is_feat_gcs_supported()) && (GET_RW(ep->spsr) == MODE_RW_64)) {
519 scr_el3 |= SCR_GCSEn_BIT;
520 }
521
522 /*
523 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
524 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
525 * next mode is Hyp.
526 * SCR_EL3.FGTEn: Enable Fine Grained Virtualization Traps under the
527 * same conditions as HVC instructions and when the processor supports
528 * ARMv8.6-FGT.
529 * SCR_EL3.ECVEn: Enable Enhanced Counter Virtualization (ECV)
530 * CNTPOFF_EL2 register under the same conditions as HVC instructions
531 * and when the processor supports ECV.
532 */
533 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
534 || ((GET_RW(ep->spsr) != MODE_RW_64)
535 && (GET_M32(ep->spsr) == MODE32_hyp))) {
536 scr_el3 |= SCR_HCE_BIT;
537
538 if (is_feat_fgt_supported()) {
539 scr_el3 |= SCR_FGTEN_BIT;
540 }
541
542 if (is_feat_ecv_supported()) {
543 scr_el3 |= SCR_ECVEN_BIT;
544 }
545 }
546
547 /* Enable WFE trap delay in SCR_EL3 if supported and configured */
548 if (is_feat_twed_supported()) {
549 /* Set delay in SCR_EL3 */
550 scr_el3 &= ~(SCR_TWEDEL_MASK << SCR_TWEDEL_SHIFT);
551 scr_el3 |= ((TWED_DELAY & SCR_TWEDEL_MASK)
552 << SCR_TWEDEL_SHIFT);
553
554 /* Enable WFE delay */
555 scr_el3 |= SCR_TWEDEn_BIT;
556 }
557
558 #if IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2
559 /* Enable S-EL2 if FEAT_SEL2 is implemented for all the contexts. */
560 if (is_feat_sel2_supported()) {
561 scr_el3 |= SCR_EEL2_BIT;
562 }
563 #endif /* (IMAGE_BL31 && defined(SPD_spmd) && SPMD_SPM_AT_SEL2) */
564
565 if (is_feat_mec_supported()) {
566 scr_el3 |= SCR_MECEn_BIT;
567 }
568
569 /*
570 * Populate EL3 state so that we've the right context
571 * before doing ERET
572 */
573 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
574 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
575 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
576
577 /* Start with a clean MDCR_EL3 copy as all relevant values are set */
578 mdcr_el3 = MDCR_EL3_RESET_VAL;
579
580 /* ---------------------------------------------------------------------
581 * Initialise MDCR_EL3, setting all fields rather than relying on hw.
582 * Some fields are architecturally UNKNOWN on reset.
583 *
584 * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
585 * Debug exceptions, other than Breakpoint Instruction exceptions, are
586 * disabled from all ELs in Secure state.
587 *
588 * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
589 * privileged debug from S-EL1.
590 *
591 * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
592 * access to the powerdown debug registers do not trap to EL3.
593 *
594 * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
595 * debug registers, other than those registers that are controlled by
596 * MDCR_EL3.TDOSA.
597 */
598 mdcr_el3 |= ((MDCR_SDD_BIT | MDCR_SPD32(MDCR_SPD32_DISABLE))
599 & ~(MDCR_TDA_BIT | MDCR_TDOSA_BIT)) ;
600 write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3);
601
602 #if IMAGE_BL31
603 /* Enable FEAT_TRF for Non-Secure and prohibit for Secure state. */
604 if (is_feat_trf_supported()) {
605 trf_enable(ctx);
606 }
607
608 if (is_feat_tcr2_supported()) {
609 tcr2_enable(ctx);
610 }
611
612 pmuv3_enable(ctx);
613
614 if (is_feat_idte3_supported()) {
615 idte3_enable(ctx);
616 }
617
618 #if CTX_INCLUDE_EL2_REGS && IMAGE_BL31
619 /*
620 * Initialize SCTLR_EL2 context register with reset value.
621 */
622 write_el2_ctx_common(get_el2_sysregs_ctx(ctx), sctlr_el2, SCTLR_EL2_RES1);
623 #endif /* CTX_INCLUDE_EL2_REGS */
624 #endif /* IMAGE_BL31 */
625
626 /*
627 * Store the X0-X7 value from the entrypoint into the context
628 * Use memcpy as we are in control of the layout of the structures
629 */
630 gp_regs = get_gpregs_ctx(ctx);
631 memcpy((void *)gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
632 }
633
634 /*******************************************************************************
635 * Context management library initialization routine. This library is used by
636 * runtime services to share pointers to 'cpu_context' structures for secure
637 * non-secure and realm states. Management of the structures and their associated
638 * memory is not done by the context management library e.g. the PSCI service
639 * manages the cpu context used for entry from and exit to the non-secure state.
640 * The Secure payload dispatcher service manages the context(s) corresponding to
641 * the secure state. It also uses this library to get access to the non-secure
642 * state cpu context pointers.
643 * Lastly, this library provides the API to make SP_EL3 point to the cpu context
644 * which will be used for programming an entry into a lower EL. The same context
645 * will be used to save state upon exception entry from that EL.
646 ******************************************************************************/
cm_init(void)647 void __init cm_init(void)
648 {
649 /*
650 * The context management library has only global data to initialize, but
651 * that will be done when the BSS is zeroed out.
652 */
653 }
654
655 /*******************************************************************************
656 * This is the high-level function used to initialize the cpu_context 'ctx' for
657 * first use. It performs initializations that are common to all security states
658 * and initializations specific to the security state specified in 'ep'
659 ******************************************************************************/
cm_setup_context(cpu_context_t * ctx,const entry_point_info_t * ep)660 void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
661 {
662 size_t security_state;
663
664 assert(ctx != NULL);
665
666 /*
667 * Perform initializations that are common
668 * to all security states
669 */
670 setup_context_common(ctx, ep);
671
672 security_state = GET_SECURITY_STATE(ep->h.attr);
673
674 /* Perform security state specific initializations */
675 switch (security_state) {
676 case SECURE:
677 setup_secure_context(ctx, ep);
678 break;
679 #if ENABLE_RME && IMAGE_BL31
680 case REALM:
681 setup_realm_context(ctx, ep);
682 break;
683 #endif
684 case NON_SECURE:
685 setup_ns_context(ctx, ep);
686 break;
687 default:
688 ERROR("Invalid security state\n");
689 panic();
690 break;
691 }
692 }
693
694 /*******************************************************************************
695 * Enable architecture extensions for EL3 execution. This function only updates
696 * registers in-place which are expected to either never change or be
697 * overwritten by el3_exit. Expects the core_pos of the current core as argument.
698 ******************************************************************************/
cm_manage_extensions_el3(unsigned int my_idx)699 void __no_pauth cm_manage_extensions_el3(unsigned int my_idx)
700 {
701 if (is_feat_pauth_supported()) {
702 pauth_init_enable_el3();
703 }
704
705 #if IMAGE_BL31
706 if (is_feat_sve_supported()) {
707 sve_init_el3();
708 }
709
710 if (is_feat_amu_supported()) {
711 amu_init_el3(my_idx);
712 }
713
714 if (is_feat_sme_supported()) {
715 sme_init_el3();
716 }
717
718 if (is_feat_fgwte3_supported()) {
719 write_fgwte3_el3(FGWTE3_EL3_EARLY_INIT_VAL);
720 }
721
722 if (is_feat_mpam_supported()) {
723 mpam_init_el3();
724 }
725
726 if (is_feat_cpa2_supported()) {
727 cpa2_enable_el3();
728 }
729
730 pmuv3_init_el3();
731 #endif /* IMAGE_BL31 */
732 }
733
734 /******************************************************************************
735 * Function to initialise the registers with the RESET values in the context
736 * memory, which are maintained per world.
737 ******************************************************************************/
cm_el3_arch_init_per_world(per_world_context_t * per_world_ctx)738 static void cm_el3_arch_init_per_world(per_world_context_t *per_world_ctx)
739 {
740 per_world_ctx->ctx_cptr_el3 = CPTR_EL3_RESET_VAL;
741 per_world_ctx->ctx_mpam3_el3 = MPAM3_EL3_RESET_VAL;
742 }
743
744 /*******************************************************************************
745 * Initialise per_world_context for Non-Secure world.
746 * This function enables the architecture extensions, which have same value
747 * across the cores for the non-secure world.
748 ******************************************************************************/
manage_extensions_nonsecure_per_world(void)749 static void manage_extensions_nonsecure_per_world(void)
750 {
751 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_NS]);
752
753 #if IMAGE_BL31
754 if (is_feat_sme_supported()) {
755 sme_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
756 }
757
758 if (is_feat_sve_supported()) {
759 sve_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
760 }
761
762 if (is_feat_amu_supported()) {
763 amu_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
764 }
765
766 if (is_feat_sys_reg_trace_supported()) {
767 sys_reg_trace_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
768 }
769
770 if (is_feat_mpam_supported()) {
771 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_NS]);
772 }
773
774 if (is_feat_idte3_supported()) {
775 idte3_init_cached_idregs_per_world(CPU_CONTEXT_NS);
776 }
777 #endif /* IMAGE_BL31 */
778 }
779
780 /*******************************************************************************
781 * Initialise per_world_context for Secure world.
782 * This function enables the architecture extensions, which have same value
783 * across the cores for the secure world.
784 ******************************************************************************/
manage_extensions_secure_per_world(void)785 static void manage_extensions_secure_per_world(void)
786 {
787 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
788
789 #if IMAGE_BL31
790 if (is_feat_sme_supported()) {
791
792 if (ENABLE_SME_FOR_SWD) {
793 /*
794 * Enable SME, SVE, FPU/SIMD in secure context, SPM must ensure
795 * SME, SVE, and FPU/SIMD context properly managed.
796 */
797 sme_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
798 } else {
799 /*
800 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
801 * world can safely use the associated registers.
802 */
803 sme_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
804 }
805 }
806 if (is_feat_sve_supported()) {
807 if (ENABLE_SVE_FOR_SWD) {
808 /*
809 * Enable SVE and FPU in secure context, SPM must ensure
810 * that the SVE and FPU register contexts are properly managed.
811 */
812 sve_enable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
813 } else {
814 /*
815 * Disable SVE and FPU in secure context so non-secure world
816 * can safely use them.
817 */
818 sve_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
819 }
820 }
821
822 /* NS can access this but Secure shouldn't */
823 if (is_feat_sys_reg_trace_supported()) {
824 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_SECURE]);
825 }
826
827 if (is_feat_idte3_supported()) {
828 idte3_init_cached_idregs_per_world(CPU_CONTEXT_SECURE);
829 }
830 #endif /* IMAGE_BL31 */
831 }
832
manage_extensions_realm_per_world(void)833 static void manage_extensions_realm_per_world(void)
834 {
835 #if ENABLE_RME && IMAGE_BL31
836 cm_el3_arch_init_per_world(&per_world_context[CPU_CONTEXT_REALM]);
837
838 if (is_feat_sve_supported()) {
839 /*
840 * Enable SVE and FPU in realm context when it is enabled for NS.
841 * Realm manager must ensure that the SVE and FPU register
842 * contexts are properly managed.
843 */
844 sve_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
845 }
846
847 /* NS can access this but Realm shouldn't */
848 if (is_feat_sys_reg_trace_supported()) {
849 sys_reg_trace_disable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
850 }
851
852 /*
853 * If SME/SME2 is supported and enabled for NS world, then disable trapping
854 * of SME instructions for Realm world. RMM will save/restore required
855 * registers that are shared with SVE/FPU so that Realm can use FPU or SVE.
856 */
857 if (is_feat_sme_supported()) {
858 sme_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
859 }
860
861 /*
862 * If FEAT_MPAM is supported and enabled, then disable trapping access
863 * to the MPAM registers for Realm world. Instead, RMM will configure
864 * the access to be trapped by itself so it can inject undefined aborts
865 * back to the Realm.
866 */
867 if (is_feat_mpam_supported()) {
868 mpam_enable_per_world(&per_world_context[CPU_CONTEXT_REALM]);
869 }
870
871 if (is_feat_idte3_supported()) {
872 idte3_init_cached_idregs_per_world(CPU_CONTEXT_REALM);
873 }
874 #endif /* ENABLE_RME && IMAGE_BL31 */
875 }
876
cm_manage_extensions_per_world(void)877 void cm_manage_extensions_per_world(void)
878 {
879 manage_extensions_nonsecure_per_world();
880 manage_extensions_secure_per_world();
881 manage_extensions_realm_per_world();
882 }
883
cm_init_percpu_once_regs(void)884 void cm_init_percpu_once_regs(void)
885 {
886 #if IMAGE_BL31
887 if (is_feat_idte3_supported()) {
888 idte3_init_percpu_once_regs(CPU_CONTEXT_NS);
889 idte3_init_percpu_once_regs(CPU_CONTEXT_SECURE);
890 #if ENABLE_RME
891 idte3_init_percpu_once_regs(CPU_CONTEXT_REALM);
892 #endif /* ENABLE_RME */
893 }
894 #endif /* IMAGE_BL31 */
895 }
896
897 /*******************************************************************************
898 * Enable architecture extensions on first entry to Non-secure world.
899 ******************************************************************************/
manage_extensions_nonsecure(cpu_context_t * ctx)900 static void manage_extensions_nonsecure(cpu_context_t *ctx)
901 {
902 #if IMAGE_BL31
903 /* NOTE: registers are not context switched */
904 if (is_feat_amu_supported()) {
905 amu_enable(ctx);
906 }
907
908 if (is_feat_sme_supported()) {
909 sme_enable(ctx);
910 }
911
912 if (is_feat_fgt2_supported()) {
913 fgt2_enable(ctx);
914 }
915
916 if (is_feat_debugv8p9_supported()) {
917 debugv8p9_extended_bp_wp_enable(ctx);
918 }
919
920 if (is_feat_spe_supported()) {
921 spe_enable_ns(ctx);
922 }
923
924 if (is_feat_trbe_supported()) {
925 if (check_if_trbe_disable_affected_core()) {
926 trbe_disable_ns(ctx);
927 } else {
928 trbe_enable_ns(ctx);
929 }
930 }
931
932 if (is_feat_brbe_supported()) {
933 brbe_enable(ctx);
934 }
935 #endif /* IMAGE_BL31 */
936 }
937
938 #if INIT_UNUSED_NS_EL2
939 /*******************************************************************************
940 * Enable architecture extensions in-place at EL2 on first entry to Non-secure
941 * world when EL2 is empty and unused.
942 ******************************************************************************/
manage_extensions_nonsecure_el2_unused(void)943 static void manage_extensions_nonsecure_el2_unused(void)
944 {
945 #if IMAGE_BL31
946 if (is_feat_spe_supported()) {
947 spe_init_el2_unused();
948 }
949
950 if (is_feat_amu_supported()) {
951 amu_init_el2_unused();
952 }
953
954 if (is_feat_mpam_supported()) {
955 mpam_init_el2_unused();
956 }
957
958 if (is_feat_trbe_supported()) {
959 trbe_init_el2_unused();
960 }
961
962 if (is_feat_sys_reg_trace_supported()) {
963 sys_reg_trace_init_el2_unused();
964 }
965
966 if (is_feat_trf_supported()) {
967 trf_init_el2_unused();
968 }
969
970 pmuv3_init_el2_unused();
971
972 if (is_feat_sve_supported()) {
973 sve_init_el2_unused();
974 }
975
976 if (is_feat_sme_supported()) {
977 sme_init_el2_unused();
978 }
979
980 if (is_feat_mops_supported() && is_feat_hcx_supported()) {
981 write_hcrx_el2(read_hcrx_el2() | HCRX_EL2_MSCEn_BIT);
982 }
983
984 if (is_feat_pauth_supported()) {
985 pauth_enable_el2();
986 }
987 #endif /* IMAGE_BL31 */
988 }
989 #endif /* INIT_UNUSED_NS_EL2 */
990
991 /*******************************************************************************
992 * Enable architecture extensions on first entry to Secure world.
993 ******************************************************************************/
manage_extensions_secure(cpu_context_t * ctx)994 static void manage_extensions_secure(cpu_context_t *ctx)
995 {
996 #if IMAGE_BL31
997 if (is_feat_sme_supported()) {
998 if (ENABLE_SME_FOR_SWD) {
999 /*
1000 * Enable SME, SVE, FPU/SIMD in secure context, secure manager
1001 * must ensure SME, SVE, and FPU/SIMD context properly managed.
1002 */
1003 sme_init_el3();
1004 sme_enable(ctx);
1005 } else {
1006 /*
1007 * Disable SME, SVE, FPU/SIMD in secure context so non-secure
1008 * world can safely use the associated registers.
1009 */
1010 sme_disable(ctx);
1011 }
1012 }
1013
1014 if (is_feat_spe_supported()) {
1015 spe_disable_secure(ctx);
1016 }
1017
1018 if (is_feat_trbe_supported()) {
1019 trbe_disable_secure(ctx);
1020 }
1021 #endif /* IMAGE_BL31 */
1022 }
1023
1024 /*******************************************************************************
1025 * The following function initializes the cpu_context for the current CPU
1026 * for first use, and sets the initial entrypoint state as specified by the
1027 * entry_point_info structure.
1028 ******************************************************************************/
cm_init_my_context(const entry_point_info_t * ep)1029 void cm_init_my_context(const entry_point_info_t *ep)
1030 {
1031 cpu_context_t *ctx;
1032 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
1033 cm_setup_context(ctx, ep);
1034 }
1035
1036 /* EL2 present but unused, need to disable safely. SCTLR_EL2 can be ignored */
init_nonsecure_el2_unused(cpu_context_t * ctx)1037 static void init_nonsecure_el2_unused(cpu_context_t *ctx)
1038 {
1039 #if INIT_UNUSED_NS_EL2
1040 u_register_t hcr_el2 = HCR_RESET_VAL;
1041 u_register_t mdcr_el2;
1042 u_register_t scr_el3;
1043
1044 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
1045
1046 /* Set EL2 register width: Set HCR_EL2.RW to match SCR_EL3.RW */
1047 if ((scr_el3 & SCR_RW_BIT) != 0U) {
1048 hcr_el2 |= HCR_RW_BIT;
1049 }
1050
1051 write_hcr_el2(hcr_el2);
1052
1053 /*
1054 * Initialise CPTR_EL2 setting all fields rather than relying on the hw.
1055 * All fields have architecturally UNKNOWN reset values.
1056 */
1057 write_cptr_el2(CPTR_EL2_RESET_VAL);
1058
1059 /*
1060 * Initialise CNTHCTL_EL2. All fields are architecturally UNKNOWN on
1061 * reset and are set to zero except for field(s) listed below.
1062 *
1063 * CNTHCTL_EL2.EL1PTEN: Set to one to disable traps to Hyp mode of
1064 * Non-secure EL0 and EL1 accesses to the physical timer registers.
1065 *
1066 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to Hyp mode of
1067 * Non-secure EL0 and EL1 accesses to the physical counter registers.
1068 */
1069 write_cnthctl_el2(CNTHCTL_RESET_VAL | EL1PCEN_BIT | EL1PCTEN_BIT);
1070
1071 /*
1072 * Initialise CNTVOFF_EL2 to zero as it resets to an architecturally
1073 * UNKNOWN value.
1074 */
1075 write_cntvoff_el2(0);
1076
1077 /*
1078 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and MPIDR_EL1
1079 * respectively.
1080 */
1081 write_vpidr_el2(read_midr_el1());
1082 write_vmpidr_el2(read_mpidr_el1());
1083
1084 /*
1085 * Initialise VTTBR_EL2. All fields are architecturally UNKNOWN on reset.
1086 *
1087 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage 2 address
1088 * translation is disabled, cache maintenance operations depend on the
1089 * VMID.
1090 *
1091 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address translation is
1092 * disabled.
1093 */
1094 write_vttbr_el2(VTTBR_RESET_VAL &
1095 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT) |
1096 (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
1097
1098 /*
1099 * Initialise MDCR_EL2, setting all fields rather than relying on hw.
1100 * Some fields are architecturally UNKNOWN on reset.
1101 *
1102 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and EL1 System
1103 * register accesses to the Debug ROM registers are not trapped to EL2.
1104 *
1105 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1 System register
1106 * accesses to the powerdown debug registers are not trapped to EL2.
1107 *
1108 * MDCR_EL2.TDA: Set to zero so that System register accesses to the
1109 * debug registers do not trap to EL2.
1110 *
1111 * MDCR_EL2.TDE: Set to zero so that debug exceptions are not routed to
1112 * EL2.
1113 */
1114 mdcr_el2 = MDCR_EL2_RESET_VAL &
1115 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT | MDCR_EL2_TDA_BIT |
1116 MDCR_EL2_TDE_BIT);
1117
1118 write_mdcr_el2(mdcr_el2);
1119
1120 /*
1121 * Initialise HSTR_EL2. All fields are architecturally UNKNOWN on reset.
1122 *
1123 * HSTR_EL2.T<n>: Set all these fields to zero so that Non-secure EL0 or
1124 * EL1 accesses to System registers do not trap to EL2.
1125 */
1126 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
1127
1128 /*
1129 * Initialise CNTHP_CTL_EL2. All fields are architecturally UNKNOWN on
1130 * reset.
1131 *
1132 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2 physical timer
1133 * and prevent timer interrupts.
1134 */
1135 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT));
1136
1137 manage_extensions_nonsecure_el2_unused();
1138 #endif /* INIT_UNUSED_NS_EL2 */
1139 }
1140
1141 /*******************************************************************************
1142 * Prepare the CPU system registers for first entry into realm, secure, or
1143 * normal world.
1144 *
1145 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
1146 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
1147 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
1148 * For all entries, the EL1 registers are initialized from the cpu_context
1149 ******************************************************************************/
cm_prepare_el3_exit(size_t security_state)1150 void cm_prepare_el3_exit(size_t security_state)
1151 {
1152 u_register_t sctlr_el2, scr_el3;
1153 cpu_context_t *ctx = cm_get_context(security_state);
1154
1155 assert(ctx != NULL);
1156
1157 if (security_state == NON_SECURE) {
1158 uint64_t el2_implemented = el_implemented(2);
1159
1160 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx),
1161 CTX_SCR_EL3);
1162
1163 if (el2_implemented != EL_IMPL_NONE) {
1164
1165 /*
1166 * If context is not being used for EL2, initialize
1167 * HCRX_EL2 with its init value here.
1168 */
1169 if (is_feat_hcx_supported()) {
1170 write_hcrx_el2(HCRX_EL2_INIT_VAL);
1171 }
1172
1173 /*
1174 * Initialize Fine-grained trap registers introduced
1175 * by FEAT_FGT so all traps are initially disabled when
1176 * switching to EL2 or a lower EL, preventing undesired
1177 * behavior.
1178 */
1179 if (is_feat_fgt_supported()) {
1180 /*
1181 * Initialize HFG*_EL2 registers with a default
1182 * value so legacy systems unaware of FEAT_FGT
1183 * do not get trapped due to their lack of
1184 * initialization for this feature.
1185 */
1186 write_hfgitr_el2(HFGITR_EL2_INIT_VAL);
1187 write_hfgrtr_el2(HFGRTR_EL2_INIT_VAL);
1188 write_hfgwtr_el2(HFGWTR_EL2_INIT_VAL);
1189 }
1190
1191 /* Condition to ensure EL2 is being used. */
1192 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
1193 /* Initialize SCTLR_EL2 register with reset value. */
1194 sctlr_el2 = SCTLR_EL2_RES1;
1195
1196 /*
1197 * If workaround of errata 764081 for Cortex-A75
1198 * is used then set SCTLR_EL2.IESB to enable
1199 * Implicit Error Synchronization Barrier.
1200 */
1201 if (errata_a75_764081_applies()) {
1202 sctlr_el2 |= SCTLR_IESB_BIT;
1203 }
1204
1205 write_sctlr_el2(sctlr_el2);
1206 } else {
1207 /*
1208 * (scr_el3 & SCR_HCE_BIT==0)
1209 * EL2 implemented but unused.
1210 */
1211 init_nonsecure_el2_unused(ctx);
1212 }
1213 }
1214
1215 if (is_feat_fgwte3_supported()) {
1216 /*
1217 * TCR_EL3 and ACTLR_EL3 could be overwritten
1218 * by platforms and hence is locked a bit late.
1219 */
1220 write_fgwte3_el3(FGWTE3_EL3_LATE_INIT_VAL);
1221 }
1222 }
1223 #if !CTX_INCLUDE_EL2_REGS || IMAGE_BL1
1224 /* Restore EL1 system registers, only when CTX_INCLUDE_EL2_REGS=0 */
1225 cm_el1_sysregs_context_restore(security_state);
1226 #endif
1227 cm_set_next_eret_context(security_state);
1228 }
1229
1230 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
1231
el2_sysregs_context_save_fgt(el2_sysregs_t * ctx)1232 static void el2_sysregs_context_save_fgt(el2_sysregs_t *ctx)
1233 {
1234 write_el2_ctx_fgt(ctx, hdfgrtr_el2, read_hdfgrtr_el2());
1235 if (is_feat_amu_supported()) {
1236 write_el2_ctx_fgt(ctx, hafgrtr_el2, read_hafgrtr_el2());
1237 }
1238 write_el2_ctx_fgt(ctx, hdfgwtr_el2, read_hdfgwtr_el2());
1239 write_el2_ctx_fgt(ctx, hfgitr_el2, read_hfgitr_el2());
1240 write_el2_ctx_fgt(ctx, hfgrtr_el2, read_hfgrtr_el2());
1241 write_el2_ctx_fgt(ctx, hfgwtr_el2, read_hfgwtr_el2());
1242 }
1243
el2_sysregs_context_restore_fgt(el2_sysregs_t * ctx)1244 static void el2_sysregs_context_restore_fgt(el2_sysregs_t *ctx)
1245 {
1246 write_hdfgrtr_el2(read_el2_ctx_fgt(ctx, hdfgrtr_el2));
1247 if (is_feat_amu_supported()) {
1248 write_hafgrtr_el2(read_el2_ctx_fgt(ctx, hafgrtr_el2));
1249 }
1250 write_hdfgwtr_el2(read_el2_ctx_fgt(ctx, hdfgwtr_el2));
1251 write_hfgitr_el2(read_el2_ctx_fgt(ctx, hfgitr_el2));
1252 write_hfgrtr_el2(read_el2_ctx_fgt(ctx, hfgrtr_el2));
1253 write_hfgwtr_el2(read_el2_ctx_fgt(ctx, hfgwtr_el2));
1254 }
1255
el2_sysregs_context_save_fgt2(el2_sysregs_t * ctx)1256 static void el2_sysregs_context_save_fgt2(el2_sysregs_t *ctx)
1257 {
1258 write_el2_ctx_fgt2(ctx, hdfgrtr2_el2, read_hdfgrtr2_el2());
1259 write_el2_ctx_fgt2(ctx, hdfgwtr2_el2, read_hdfgwtr2_el2());
1260 write_el2_ctx_fgt2(ctx, hfgitr2_el2, read_hfgitr2_el2());
1261 write_el2_ctx_fgt2(ctx, hfgrtr2_el2, read_hfgrtr2_el2());
1262 write_el2_ctx_fgt2(ctx, hfgwtr2_el2, read_hfgwtr2_el2());
1263 }
1264
el2_sysregs_context_restore_fgt2(el2_sysregs_t * ctx)1265 static void el2_sysregs_context_restore_fgt2(el2_sysregs_t *ctx)
1266 {
1267 write_hdfgrtr2_el2(read_el2_ctx_fgt2(ctx, hdfgrtr2_el2));
1268 write_hdfgwtr2_el2(read_el2_ctx_fgt2(ctx, hdfgwtr2_el2));
1269 write_hfgitr2_el2(read_el2_ctx_fgt2(ctx, hfgitr2_el2));
1270 write_hfgrtr2_el2(read_el2_ctx_fgt2(ctx, hfgrtr2_el2));
1271 write_hfgwtr2_el2(read_el2_ctx_fgt2(ctx, hfgwtr2_el2));
1272 }
1273
el2_sysregs_context_save_mpam(el2_sysregs_t * ctx)1274 static void el2_sysregs_context_save_mpam(el2_sysregs_t *ctx)
1275 {
1276 u_register_t mpam_idr = read_mpamidr_el1();
1277
1278 write_el2_ctx_mpam(ctx, mpam2_el2, read_mpam2_el2());
1279
1280 /*
1281 * The context registers that we intend to save would be part of the
1282 * PE's system register frame only if MPAMIDR_EL1.HAS_HCR == 1.
1283 */
1284 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1285 return;
1286 }
1287
1288 /*
1289 * MPAMHCR_EL2, MPAMVPMV_EL2 and MPAMVPM0_EL2 are always present if
1290 * MPAMIDR_HAS_HCR_BIT == 1.
1291 */
1292 write_el2_ctx_mpam(ctx, mpamhcr_el2, read_mpamhcr_el2());
1293 write_el2_ctx_mpam(ctx, mpamvpm0_el2, read_mpamvpm0_el2());
1294 write_el2_ctx_mpam(ctx, mpamvpmv_el2, read_mpamvpmv_el2());
1295
1296 /*
1297 * The number of MPAMVPM registers is implementation defined, their
1298 * number is stored in the MPAMIDR_EL1 register.
1299 */
1300 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1301 case 7:
1302 write_el2_ctx_mpam(ctx, mpamvpm7_el2, read_mpamvpm7_el2());
1303 __fallthrough;
1304 case 6:
1305 write_el2_ctx_mpam(ctx, mpamvpm6_el2, read_mpamvpm6_el2());
1306 __fallthrough;
1307 case 5:
1308 write_el2_ctx_mpam(ctx, mpamvpm5_el2, read_mpamvpm5_el2());
1309 __fallthrough;
1310 case 4:
1311 write_el2_ctx_mpam(ctx, mpamvpm4_el2, read_mpamvpm4_el2());
1312 __fallthrough;
1313 case 3:
1314 write_el2_ctx_mpam(ctx, mpamvpm3_el2, read_mpamvpm3_el2());
1315 __fallthrough;
1316 case 2:
1317 write_el2_ctx_mpam(ctx, mpamvpm2_el2, read_mpamvpm2_el2());
1318 __fallthrough;
1319 case 1:
1320 write_el2_ctx_mpam(ctx, mpamvpm1_el2, read_mpamvpm1_el2());
1321 break;
1322 }
1323 }
1324
el2_sysregs_context_restore_mpam(el2_sysregs_t * ctx)1325 static void el2_sysregs_context_restore_mpam(el2_sysregs_t *ctx)
1326 {
1327 u_register_t mpam_idr = read_mpamidr_el1();
1328
1329 write_mpam2_el2(read_el2_ctx_mpam(ctx, mpam2_el2));
1330
1331 if ((mpam_idr & MPAMIDR_HAS_HCR_BIT) == 0U) {
1332 return;
1333 }
1334
1335 write_mpamhcr_el2(read_el2_ctx_mpam(ctx, mpamhcr_el2));
1336 write_mpamvpm0_el2(read_el2_ctx_mpam(ctx, mpamvpm0_el2));
1337 write_mpamvpmv_el2(read_el2_ctx_mpam(ctx, mpamvpmv_el2));
1338
1339 switch ((mpam_idr >> MPAMIDR_EL1_VPMR_MAX_SHIFT) & MPAMIDR_EL1_VPMR_MAX_MASK) {
1340 case 7:
1341 write_mpamvpm7_el2(read_el2_ctx_mpam(ctx, mpamvpm7_el2));
1342 __fallthrough;
1343 case 6:
1344 write_mpamvpm6_el2(read_el2_ctx_mpam(ctx, mpamvpm6_el2));
1345 __fallthrough;
1346 case 5:
1347 write_mpamvpm5_el2(read_el2_ctx_mpam(ctx, mpamvpm5_el2));
1348 __fallthrough;
1349 case 4:
1350 write_mpamvpm4_el2(read_el2_ctx_mpam(ctx, mpamvpm4_el2));
1351 __fallthrough;
1352 case 3:
1353 write_mpamvpm3_el2(read_el2_ctx_mpam(ctx, mpamvpm3_el2));
1354 __fallthrough;
1355 case 2:
1356 write_mpamvpm2_el2(read_el2_ctx_mpam(ctx, mpamvpm2_el2));
1357 __fallthrough;
1358 case 1:
1359 write_mpamvpm1_el2(read_el2_ctx_mpam(ctx, mpamvpm1_el2));
1360 break;
1361 }
1362 }
1363
1364 /* ---------------------------------------------------------------------------
1365 * The following registers are not added:
1366 * ICH_AP0R<n>_EL2
1367 * ICH_AP1R<n>_EL2
1368 * ICH_LR<n>_EL2
1369 *
1370 * NOTE: For a system with S-EL2 present but not enabled, accessing
1371 * ICC_SRE_EL2 is undefined from EL3. To workaround this change the
1372 * SCR_EL3.NS = 1 before accessing this register.
1373 * ---------------------------------------------------------------------------
1374 */
el2_sysregs_context_save_gic(el2_sysregs_t * ctx,uint32_t security_state)1375 static void el2_sysregs_context_save_gic(el2_sysregs_t *ctx, uint32_t security_state)
1376 {
1377 u_register_t scr_el3 = read_scr_el3();
1378
1379 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
1380 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2());
1381 #else
1382 write_scr_el3(scr_el3 | SCR_NS_BIT);
1383 isb();
1384
1385 write_el2_ctx_common(ctx, icc_sre_el2, read_icc_sre_el2());
1386
1387 write_scr_el3(scr_el3);
1388 isb();
1389 #endif
1390 write_el2_ctx_common(ctx, ich_hcr_el2, read_ich_hcr_el2());
1391
1392 if (errata_ich_vmcr_el2_applies()) {
1393 if (security_state == SECURE) {
1394 write_scr_el3(scr_el3 & ~SCR_NS_BIT);
1395 } else {
1396 write_scr_el3(scr_el3 | SCR_NS_BIT);
1397 }
1398 isb();
1399 }
1400
1401 write_el2_ctx_common(ctx, ich_vmcr_el2, read_ich_vmcr_el2());
1402
1403 if (errata_ich_vmcr_el2_applies()) {
1404 write_scr_el3(scr_el3);
1405 isb();
1406 }
1407 }
1408
el2_sysregs_context_restore_gic(el2_sysregs_t * ctx,uint32_t security_state)1409 static void el2_sysregs_context_restore_gic(el2_sysregs_t *ctx, uint32_t security_state)
1410 {
1411 u_register_t scr_el3 = read_scr_el3();
1412
1413 #if defined(SPD_spmd) && SPMD_SPM_AT_SEL2
1414 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
1415 #else
1416 write_scr_el3(scr_el3 | SCR_NS_BIT);
1417 isb();
1418
1419 write_icc_sre_el2(read_el2_ctx_common(ctx, icc_sre_el2));
1420
1421 write_scr_el3(scr_el3);
1422 isb();
1423 #endif
1424 write_ich_hcr_el2(read_el2_ctx_common(ctx, ich_hcr_el2));
1425
1426 if (errata_ich_vmcr_el2_applies()) {
1427 if (security_state == SECURE) {
1428 write_scr_el3(scr_el3 & ~SCR_NS_BIT);
1429 } else {
1430 write_scr_el3(scr_el3 | SCR_NS_BIT);
1431 }
1432 isb();
1433 }
1434
1435 write_ich_vmcr_el2(read_el2_ctx_common(ctx, ich_vmcr_el2));
1436
1437 if (errata_ich_vmcr_el2_applies()) {
1438 write_scr_el3(scr_el3);
1439 isb();
1440 }
1441 }
1442
1443 /* -----------------------------------------------------
1444 * The following registers are not added:
1445 * AMEVCNTVOFF0<n>_EL2
1446 * AMEVCNTVOFF1<n>_EL2
1447 * -----------------------------------------------------
1448 */
el2_sysregs_context_save_common(el2_sysregs_t * ctx)1449 static void el2_sysregs_context_save_common(el2_sysregs_t *ctx)
1450 {
1451 write_el2_ctx_common(ctx, actlr_el2, read_actlr_el2());
1452 write_el2_ctx_common(ctx, afsr0_el2, read_afsr0_el2());
1453 write_el2_ctx_common(ctx, afsr1_el2, read_afsr1_el2());
1454 write_el2_ctx_common(ctx, amair_el2, read_amair_el2());
1455 write_el2_ctx_common(ctx, cnthctl_el2, read_cnthctl_el2());
1456 write_el2_ctx_common(ctx, cntvoff_el2, read_cntvoff_el2());
1457 write_el2_ctx_common(ctx, cptr_el2, read_cptr_el2());
1458 if (CTX_INCLUDE_AARCH32_REGS) {
1459 write_el2_ctx_common(ctx, dbgvcr32_el2, read_dbgvcr32_el2());
1460 }
1461 write_el2_ctx_common(ctx, elr_el2, read_elr_el2());
1462 write_el2_ctx_common(ctx, esr_el2, read_esr_el2());
1463 write_el2_ctx_common(ctx, far_el2, read_far_el2());
1464 write_el2_ctx_common(ctx, hacr_el2, read_hacr_el2());
1465 write_el2_ctx_common(ctx, hcr_el2, read_hcr_el2());
1466 write_el2_ctx_common(ctx, hpfar_el2, read_hpfar_el2());
1467 write_el2_ctx_common(ctx, hstr_el2, read_hstr_el2());
1468 write_el2_ctx_common(ctx, mair_el2, read_mair_el2());
1469 write_el2_ctx_common(ctx, mdcr_el2, read_mdcr_el2());
1470 write_el2_ctx_common(ctx, sctlr_el2, read_sctlr_el2());
1471 write_el2_ctx_common(ctx, spsr_el2, read_spsr_el2());
1472 write_el2_ctx_common(ctx, sp_el2, read_sp_el2());
1473 write_el2_ctx_common(ctx, tcr_el2, read_tcr_el2());
1474 write_el2_ctx_common(ctx, tpidr_el2, read_tpidr_el2());
1475 write_el2_ctx_common(ctx, vbar_el2, read_vbar_el2());
1476 write_el2_ctx_common(ctx, vmpidr_el2, read_vmpidr_el2());
1477 write_el2_ctx_common(ctx, vpidr_el2, read_vpidr_el2());
1478 write_el2_ctx_common(ctx, vtcr_el2, read_vtcr_el2());
1479
1480 write_el2_ctx_common_sysreg128(ctx, ttbr0_el2, read_ttbr0_el2());
1481 write_el2_ctx_common_sysreg128(ctx, vttbr_el2, read_vttbr_el2());
1482 }
1483
el2_sysregs_context_restore_common(el2_sysregs_t * ctx)1484 static void el2_sysregs_context_restore_common(el2_sysregs_t *ctx)
1485 {
1486 write_actlr_el2(read_el2_ctx_common(ctx, actlr_el2));
1487 write_afsr0_el2(read_el2_ctx_common(ctx, afsr0_el2));
1488 write_afsr1_el2(read_el2_ctx_common(ctx, afsr1_el2));
1489 write_amair_el2(read_el2_ctx_common(ctx, amair_el2));
1490 write_cnthctl_el2(read_el2_ctx_common(ctx, cnthctl_el2));
1491 write_cntvoff_el2(read_el2_ctx_common(ctx, cntvoff_el2));
1492 write_cptr_el2(read_el2_ctx_common(ctx, cptr_el2));
1493 if (CTX_INCLUDE_AARCH32_REGS) {
1494 write_dbgvcr32_el2(read_el2_ctx_common(ctx, dbgvcr32_el2));
1495 }
1496 write_elr_el2(read_el2_ctx_common(ctx, elr_el2));
1497 write_esr_el2(read_el2_ctx_common(ctx, esr_el2));
1498 write_far_el2(read_el2_ctx_common(ctx, far_el2));
1499 write_hacr_el2(read_el2_ctx_common(ctx, hacr_el2));
1500 write_hcr_el2(read_el2_ctx_common(ctx, hcr_el2));
1501 write_hpfar_el2(read_el2_ctx_common(ctx, hpfar_el2));
1502 write_hstr_el2(read_el2_ctx_common(ctx, hstr_el2));
1503 write_mair_el2(read_el2_ctx_common(ctx, mair_el2));
1504 write_mdcr_el2(read_el2_ctx_common(ctx, mdcr_el2));
1505 write_sctlr_el2(read_el2_ctx_common(ctx, sctlr_el2));
1506 write_spsr_el2(read_el2_ctx_common(ctx, spsr_el2));
1507 write_sp_el2(read_el2_ctx_common(ctx, sp_el2));
1508 write_tcr_el2(read_el2_ctx_common(ctx, tcr_el2));
1509 write_tpidr_el2(read_el2_ctx_common(ctx, tpidr_el2));
1510 write_ttbr0_el2(read_el2_ctx_common(ctx, ttbr0_el2));
1511 write_vbar_el2(read_el2_ctx_common(ctx, vbar_el2));
1512 write_vmpidr_el2(read_el2_ctx_common(ctx, vmpidr_el2));
1513 write_vpidr_el2(read_el2_ctx_common(ctx, vpidr_el2));
1514 write_vtcr_el2(read_el2_ctx_common(ctx, vtcr_el2));
1515 write_vttbr_el2(read_el2_ctx_common(ctx, vttbr_el2));
1516 }
1517
1518 /*******************************************************************************
1519 * Save EL2 sysreg context
1520 ******************************************************************************/
cm_el2_sysregs_context_save(uint32_t security_state)1521 void cm_el2_sysregs_context_save(uint32_t security_state)
1522 {
1523 cpu_context_t *ctx;
1524 el2_sysregs_t *el2_sysregs_ctx;
1525
1526 ctx = cm_get_context(security_state);
1527 assert(ctx != NULL);
1528
1529 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
1530
1531 el2_sysregs_context_save_common(el2_sysregs_ctx);
1532 el2_sysregs_context_save_gic(el2_sysregs_ctx, security_state);
1533
1534 if (is_feat_mte2_supported()) {
1535 write_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2, read_tfsr_el2());
1536 }
1537
1538 if (is_feat_mpam_supported()) {
1539 el2_sysregs_context_save_mpam(el2_sysregs_ctx);
1540 }
1541
1542 if (is_feat_fgt_supported()) {
1543 el2_sysregs_context_save_fgt(el2_sysregs_ctx);
1544 }
1545
1546 if (is_feat_fgt2_supported()) {
1547 el2_sysregs_context_save_fgt2(el2_sysregs_ctx);
1548 }
1549
1550 if (is_feat_ecv_v2_supported()) {
1551 write_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2, read_cntpoff_el2());
1552 }
1553
1554 if (is_feat_vhe_supported()) {
1555 write_el2_ctx_vhe(el2_sysregs_ctx, contextidr_el2,
1556 read_contextidr_el2());
1557 write_el2_ctx_vhe_sysreg128(el2_sysregs_ctx, ttbr1_el2, read_ttbr1_el2());
1558 }
1559
1560 if (is_feat_ras_supported()) {
1561 write_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2, read_vdisr_el2());
1562 write_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2, read_vsesr_el2());
1563 }
1564
1565 if (is_feat_nv2_supported()) {
1566 write_el2_ctx_neve(el2_sysregs_ctx, vncr_el2, read_vncr_el2());
1567 }
1568
1569 if (is_feat_trf_supported()) {
1570 write_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2, read_trfcr_el2());
1571 }
1572
1573 if (is_feat_csv2_2_supported()) {
1574 write_el2_ctx_csv2_2(el2_sysregs_ctx, scxtnum_el2,
1575 read_scxtnum_el2());
1576 }
1577
1578 if (is_feat_hcx_supported()) {
1579 write_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2, read_hcrx_el2());
1580 }
1581
1582 if (is_feat_tcr2_supported()) {
1583 write_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2, read_tcr2_el2());
1584 }
1585
1586 if (is_feat_s1pie_supported()) {
1587 write_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2, read_pire0_el2());
1588 write_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2, read_pir_el2());
1589 }
1590
1591 if (is_feat_s1poe_supported()) {
1592 write_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2, read_por_el2());
1593 }
1594
1595 if (is_feat_brbe_supported()) {
1596 write_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2, read_brbcr_el2());
1597 }
1598
1599 if (is_feat_s2pie_supported()) {
1600 write_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2, read_s2pir_el2());
1601 }
1602
1603 if (is_feat_gcs_supported()) {
1604 write_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2, read_gcscr_el2());
1605 write_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2, read_gcspr_el2());
1606 }
1607
1608 if (is_feat_sctlr2_supported()) {
1609 write_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2, read_sctlr2_el2());
1610 }
1611 }
1612
1613 /*******************************************************************************
1614 * Restore EL2 sysreg context
1615 ******************************************************************************/
cm_el2_sysregs_context_restore(uint32_t security_state)1616 void cm_el2_sysregs_context_restore(uint32_t security_state)
1617 {
1618 cpu_context_t *ctx;
1619 el2_sysregs_t *el2_sysregs_ctx;
1620
1621 ctx = cm_get_context(security_state);
1622 assert(ctx != NULL);
1623
1624 el2_sysregs_ctx = get_el2_sysregs_ctx(ctx);
1625
1626 el2_sysregs_context_restore_common(el2_sysregs_ctx);
1627 el2_sysregs_context_restore_gic(el2_sysregs_ctx, security_state);
1628
1629 if (is_feat_mte2_supported()) {
1630 write_tfsr_el2(read_el2_ctx_mte2(el2_sysregs_ctx, tfsr_el2));
1631 }
1632
1633 if (is_feat_mpam_supported()) {
1634 el2_sysregs_context_restore_mpam(el2_sysregs_ctx);
1635 }
1636
1637 if (is_feat_fgt_supported()) {
1638 el2_sysregs_context_restore_fgt(el2_sysregs_ctx);
1639 }
1640
1641 if (is_feat_fgt2_supported()) {
1642 el2_sysregs_context_restore_fgt2(el2_sysregs_ctx);
1643 }
1644
1645 if (is_feat_ecv_v2_supported()) {
1646 write_cntpoff_el2(read_el2_ctx_ecv(el2_sysregs_ctx, cntpoff_el2));
1647 }
1648
1649 if (is_feat_vhe_supported()) {
1650 write_contextidr_el2(read_el2_ctx_vhe(el2_sysregs_ctx,
1651 contextidr_el2));
1652 write_ttbr1_el2(read_el2_ctx_vhe(el2_sysregs_ctx, ttbr1_el2));
1653 }
1654
1655 if (is_feat_ras_supported()) {
1656 write_vdisr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vdisr_el2));
1657 write_vsesr_el2(read_el2_ctx_ras(el2_sysregs_ctx, vsesr_el2));
1658 }
1659
1660 if (is_feat_nv2_supported()) {
1661 write_vncr_el2(read_el2_ctx_neve(el2_sysregs_ctx, vncr_el2));
1662 }
1663
1664 if (is_feat_trf_supported()) {
1665 write_trfcr_el2(read_el2_ctx_trf(el2_sysregs_ctx, trfcr_el2));
1666 }
1667
1668 if (is_feat_csv2_2_supported()) {
1669 write_scxtnum_el2(read_el2_ctx_csv2_2(el2_sysregs_ctx,
1670 scxtnum_el2));
1671 }
1672
1673 if (is_feat_hcx_supported()) {
1674 write_hcrx_el2(read_el2_ctx_hcx(el2_sysregs_ctx, hcrx_el2));
1675 }
1676
1677 if (is_feat_tcr2_supported()) {
1678 write_tcr2_el2(read_el2_ctx_tcr2(el2_sysregs_ctx, tcr2_el2));
1679 }
1680
1681 if (is_feat_s1pie_supported()) {
1682 write_pire0_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pire0_el2));
1683 write_pir_el2(read_el2_ctx_sxpie(el2_sysregs_ctx, pir_el2));
1684 }
1685
1686 if (is_feat_s1poe_supported()) {
1687 write_por_el2(read_el2_ctx_sxpoe(el2_sysregs_ctx, por_el2));
1688 }
1689
1690 if (is_feat_s2pie_supported()) {
1691 write_s2pir_el2(read_el2_ctx_s2pie(el2_sysregs_ctx, s2pir_el2));
1692 }
1693
1694 if (is_feat_gcs_supported()) {
1695 write_gcscr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcscr_el2));
1696 write_gcspr_el2(read_el2_ctx_gcs(el2_sysregs_ctx, gcspr_el2));
1697 }
1698
1699 if (is_feat_sctlr2_supported()) {
1700 write_sctlr2_el2(read_el2_ctx_sctlr2(el2_sysregs_ctx, sctlr2_el2));
1701 }
1702
1703 if (is_feat_brbe_supported()) {
1704 write_brbcr_el2(read_el2_ctx_brbe(el2_sysregs_ctx, brbcr_el2));
1705 }
1706 }
1707 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
1708
1709 /*******************************************************************************
1710 * This function is used to exit to Non-secure world. If CTX_INCLUDE_EL2_REGS
1711 * is enabled, it restores EL1 and EL2 sysreg contexts instead of directly
1712 * updating EL1 and EL2 registers. Otherwise, it calls the generic
1713 * cm_prepare_el3_exit function.
1714 ******************************************************************************/
cm_prepare_el3_exit_ns(void)1715 void cm_prepare_el3_exit_ns(void)
1716 {
1717 #if (CTX_INCLUDE_EL2_REGS && IMAGE_BL31)
1718 #if ENABLE_ASSERTIONS
1719 cpu_context_t *ctx = cm_get_context(NON_SECURE);
1720 assert(ctx != NULL);
1721
1722 /* Assert that EL2 is used. */
1723 u_register_t scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
1724 assert(((scr_el3 & SCR_HCE_BIT) != 0UL) &&
1725 (el_implemented(2U) != EL_IMPL_NONE));
1726 #endif /* ENABLE_ASSERTIONS */
1727
1728 /* Restore EL2 sysreg contexts */
1729 cm_el2_sysregs_context_restore(NON_SECURE);
1730 cm_set_next_eret_context(NON_SECURE);
1731 #else
1732 cm_prepare_el3_exit(NON_SECURE);
1733 #endif /* (CTX_INCLUDE_EL2_REGS && IMAGE_BL31) */
1734 }
1735
1736 #if ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS)))
1737 /*******************************************************************************
1738 * The next set of six functions are used by runtime services to save and restore
1739 * EL1 context on the 'cpu_context' structure for the specified security state.
1740 ******************************************************************************/
el1_sysregs_context_save(el1_sysregs_t * ctx)1741 static void el1_sysregs_context_save(el1_sysregs_t *ctx)
1742 {
1743 write_el1_ctx_common(ctx, spsr_el1, read_spsr_el1());
1744 write_el1_ctx_common(ctx, elr_el1, read_elr_el1());
1745
1746 #if (!ERRATA_SPECULATIVE_AT)
1747 write_el1_ctx_common(ctx, sctlr_el1, read_sctlr_el1());
1748 write_el1_ctx_common(ctx, tcr_el1, read_tcr_el1());
1749 #endif /* (!ERRATA_SPECULATIVE_AT) */
1750
1751 write_el1_ctx_common(ctx, cpacr_el1, read_cpacr_el1());
1752 write_el1_ctx_common(ctx, csselr_el1, read_csselr_el1());
1753 write_el1_ctx_common(ctx, sp_el1, read_sp_el1());
1754 write_el1_ctx_common(ctx, esr_el1, read_esr_el1());
1755 write_el1_ctx_common(ctx, mair_el1, read_mair_el1());
1756 write_el1_ctx_common(ctx, amair_el1, read_amair_el1());
1757 write_el1_ctx_common(ctx, actlr_el1, read_actlr_el1());
1758 write_el1_ctx_common(ctx, tpidr_el1, read_tpidr_el1());
1759 write_el1_ctx_common(ctx, tpidr_el0, read_tpidr_el0());
1760 write_el1_ctx_common(ctx, tpidrro_el0, read_tpidrro_el0());
1761 write_el1_ctx_common(ctx, far_el1, read_far_el1());
1762 write_el1_ctx_common(ctx, afsr0_el1, read_afsr0_el1());
1763 write_el1_ctx_common(ctx, afsr1_el1, read_afsr1_el1());
1764 write_el1_ctx_common(ctx, contextidr_el1, read_contextidr_el1());
1765 write_el1_ctx_common(ctx, vbar_el1, read_vbar_el1());
1766 write_el1_ctx_common(ctx, mdccint_el1, read_mdccint_el1());
1767 write_el1_ctx_common(ctx, mdscr_el1, read_mdscr_el1());
1768
1769 write_el1_ctx_common_sysreg128(ctx, par_el1, read_par_el1());
1770 write_el1_ctx_common_sysreg128(ctx, ttbr0_el1, read_ttbr0_el1());
1771 write_el1_ctx_common_sysreg128(ctx, ttbr1_el1, read_ttbr1_el1());
1772
1773 if (CTX_INCLUDE_AARCH32_REGS) {
1774 /* Save Aarch32 registers */
1775 write_el1_ctx_aarch32(ctx, spsr_abt, read_spsr_abt());
1776 write_el1_ctx_aarch32(ctx, spsr_und, read_spsr_und());
1777 write_el1_ctx_aarch32(ctx, spsr_irq, read_spsr_irq());
1778 write_el1_ctx_aarch32(ctx, spsr_fiq, read_spsr_fiq());
1779 write_el1_ctx_aarch32(ctx, dacr32_el2, read_dacr32_el2());
1780 write_el1_ctx_aarch32(ctx, ifsr32_el2, read_ifsr32_el2());
1781 }
1782
1783 /* Save counter-timer kernel control register */
1784 write_el1_ctx_arch_timer(ctx, cntkctl_el1, read_cntkctl_el1());
1785 #if NS_TIMER_SWITCH
1786 /* Save NS Timer registers */
1787 write_el1_ctx_arch_timer(ctx, cntp_ctl_el0, read_cntp_ctl_el0());
1788 write_el1_ctx_arch_timer(ctx, cntp_cval_el0, read_cntp_cval_el0());
1789 write_el1_ctx_arch_timer(ctx, cntv_ctl_el0, read_cntv_ctl_el0());
1790 write_el1_ctx_arch_timer(ctx, cntv_cval_el0, read_cntv_cval_el0());
1791 #endif
1792
1793 if (is_feat_mte2_supported()) {
1794 write_el1_ctx_mte2(ctx, tfsre0_el1, read_tfsre0_el1());
1795 write_el1_ctx_mte2(ctx, tfsr_el1, read_tfsr_el1());
1796 write_el1_ctx_mte2(ctx, rgsr_el1, read_rgsr_el1());
1797 write_el1_ctx_mte2(ctx, gcr_el1, read_gcr_el1());
1798 }
1799
1800 if (is_feat_ras_supported()) {
1801 write_el1_ctx_ras(ctx, disr_el1, read_disr_el1());
1802 }
1803
1804 if (is_feat_s1pie_supported()) {
1805 write_el1_ctx_s1pie(ctx, pire0_el1, read_pire0_el1());
1806 write_el1_ctx_s1pie(ctx, pir_el1, read_pir_el1());
1807 }
1808
1809 if (is_feat_s1poe_supported()) {
1810 write_el1_ctx_s1poe(ctx, por_el1, read_por_el1());
1811 }
1812
1813 if (is_feat_s2poe_supported()) {
1814 write_el1_ctx_s2poe(ctx, s2por_el1, read_s2por_el1());
1815 }
1816
1817 if (is_feat_tcr2_supported()) {
1818 write_el1_ctx_tcr2(ctx, tcr2_el1, read_tcr2_el1());
1819 }
1820
1821 if (is_feat_trf_supported()) {
1822 write_el1_ctx_trf(ctx, trfcr_el1, read_trfcr_el1());
1823 }
1824
1825 if (is_feat_csv2_2_supported()) {
1826 write_el1_ctx_csv2_2(ctx, scxtnum_el0, read_scxtnum_el0());
1827 write_el1_ctx_csv2_2(ctx, scxtnum_el1, read_scxtnum_el1());
1828 }
1829
1830 if (is_feat_gcs_supported()) {
1831 write_el1_ctx_gcs(ctx, gcscr_el1, read_gcscr_el1());
1832 write_el1_ctx_gcs(ctx, gcscre0_el1, read_gcscre0_el1());
1833 write_el1_ctx_gcs(ctx, gcspr_el1, read_gcspr_el1());
1834 write_el1_ctx_gcs(ctx, gcspr_el0, read_gcspr_el0());
1835 }
1836
1837 if (is_feat_the_supported()) {
1838 write_el1_ctx_the_sysreg128(ctx, rcwmask_el1, read_rcwmask_el1());
1839 write_el1_ctx_the_sysreg128(ctx, rcwsmask_el1, read_rcwsmask_el1());
1840 }
1841
1842 if (is_feat_sctlr2_supported()) {
1843 write_el1_ctx_sctlr2(ctx, sctlr2_el1, read_sctlr2_el1());
1844 }
1845
1846 if (is_feat_ls64_accdata_supported()) {
1847 write_el1_ctx_ls64(ctx, accdata_el1, read_accdata_el1());
1848 }
1849 }
1850
el1_sysregs_context_restore(el1_sysregs_t * ctx)1851 static void el1_sysregs_context_restore(el1_sysregs_t *ctx)
1852 {
1853 write_spsr_el1(read_el1_ctx_common(ctx, spsr_el1));
1854 write_elr_el1(read_el1_ctx_common(ctx, elr_el1));
1855
1856 #if (!ERRATA_SPECULATIVE_AT)
1857 write_sctlr_el1(read_el1_ctx_common(ctx, sctlr_el1));
1858 write_tcr_el1(read_el1_ctx_common(ctx, tcr_el1));
1859 #endif /* (!ERRATA_SPECULATIVE_AT) */
1860
1861 write_cpacr_el1(read_el1_ctx_common(ctx, cpacr_el1));
1862 write_csselr_el1(read_el1_ctx_common(ctx, csselr_el1));
1863 write_sp_el1(read_el1_ctx_common(ctx, sp_el1));
1864 write_esr_el1(read_el1_ctx_common(ctx, esr_el1));
1865 write_ttbr0_el1(read_el1_ctx_common(ctx, ttbr0_el1));
1866 write_ttbr1_el1(read_el1_ctx_common(ctx, ttbr1_el1));
1867 write_mair_el1(read_el1_ctx_common(ctx, mair_el1));
1868 write_amair_el1(read_el1_ctx_common(ctx, amair_el1));
1869 write_actlr_el1(read_el1_ctx_common(ctx, actlr_el1));
1870 write_tpidr_el1(read_el1_ctx_common(ctx, tpidr_el1));
1871 write_tpidr_el0(read_el1_ctx_common(ctx, tpidr_el0));
1872 write_tpidrro_el0(read_el1_ctx_common(ctx, tpidrro_el0));
1873 write_par_el1(read_el1_ctx_common(ctx, par_el1));
1874 write_far_el1(read_el1_ctx_common(ctx, far_el1));
1875 write_afsr0_el1(read_el1_ctx_common(ctx, afsr0_el1));
1876 write_afsr1_el1(read_el1_ctx_common(ctx, afsr1_el1));
1877 write_contextidr_el1(read_el1_ctx_common(ctx, contextidr_el1));
1878 write_vbar_el1(read_el1_ctx_common(ctx, vbar_el1));
1879 write_mdccint_el1(read_el1_ctx_common(ctx, mdccint_el1));
1880 write_mdscr_el1(read_el1_ctx_common(ctx, mdscr_el1));
1881
1882 if (CTX_INCLUDE_AARCH32_REGS) {
1883 /* Restore Aarch32 registers */
1884 write_spsr_abt(read_el1_ctx_aarch32(ctx, spsr_abt));
1885 write_spsr_und(read_el1_ctx_aarch32(ctx, spsr_und));
1886 write_spsr_irq(read_el1_ctx_aarch32(ctx, spsr_irq));
1887 write_spsr_fiq(read_el1_ctx_aarch32(ctx, spsr_fiq));
1888 write_dacr32_el2(read_el1_ctx_aarch32(ctx, dacr32_el2));
1889 write_ifsr32_el2(read_el1_ctx_aarch32(ctx, ifsr32_el2));
1890 }
1891
1892 /* Restore counter-timer kernel control register */
1893 write_cntkctl_el1(read_el1_ctx_arch_timer(ctx, cntkctl_el1));
1894 #if NS_TIMER_SWITCH
1895 /* Restore NS Timer registers */
1896 write_cntp_ctl_el0(read_el1_ctx_arch_timer(ctx, cntp_ctl_el0));
1897 write_cntp_cval_el0(read_el1_ctx_arch_timer(ctx, cntp_cval_el0));
1898 write_cntv_ctl_el0(read_el1_ctx_arch_timer(ctx, cntv_ctl_el0));
1899 write_cntv_cval_el0(read_el1_ctx_arch_timer(ctx, cntv_cval_el0));
1900 #endif
1901
1902 if (is_feat_mte2_supported()) {
1903 write_tfsre0_el1(read_el1_ctx_mte2(ctx, tfsre0_el1));
1904 write_tfsr_el1(read_el1_ctx_mte2(ctx, tfsr_el1));
1905 write_rgsr_el1(read_el1_ctx_mte2(ctx, rgsr_el1));
1906 write_gcr_el1(read_el1_ctx_mte2(ctx, gcr_el1));
1907 }
1908
1909 if (is_feat_ras_supported()) {
1910 write_disr_el1(read_el1_ctx_ras(ctx, disr_el1));
1911 }
1912
1913 if (is_feat_s1pie_supported()) {
1914 write_pire0_el1(read_el1_ctx_s1pie(ctx, pire0_el1));
1915 write_pir_el1(read_el1_ctx_s1pie(ctx, pir_el1));
1916 }
1917
1918 if (is_feat_s1poe_supported()) {
1919 write_por_el1(read_el1_ctx_s1poe(ctx, por_el1));
1920 }
1921
1922 if (is_feat_s2poe_supported()) {
1923 write_s2por_el1(read_el1_ctx_s2poe(ctx, s2por_el1));
1924 }
1925
1926 if (is_feat_tcr2_supported()) {
1927 write_tcr2_el1(read_el1_ctx_tcr2(ctx, tcr2_el1));
1928 }
1929
1930 if (is_feat_trf_supported()) {
1931 write_trfcr_el1(read_el1_ctx_trf(ctx, trfcr_el1));
1932 }
1933
1934 if (is_feat_csv2_2_supported()) {
1935 write_scxtnum_el0(read_el1_ctx_csv2_2(ctx, scxtnum_el0));
1936 write_scxtnum_el1(read_el1_ctx_csv2_2(ctx, scxtnum_el1));
1937 }
1938
1939 if (is_feat_gcs_supported()) {
1940 write_gcscr_el1(read_el1_ctx_gcs(ctx, gcscr_el1));
1941 write_gcscre0_el1(read_el1_ctx_gcs(ctx, gcscre0_el1));
1942 write_gcspr_el1(read_el1_ctx_gcs(ctx, gcspr_el1));
1943 write_gcspr_el0(read_el1_ctx_gcs(ctx, gcspr_el0));
1944 }
1945
1946 if (is_feat_the_supported()) {
1947 write_rcwmask_el1(read_el1_ctx_the(ctx, rcwmask_el1));
1948 write_rcwsmask_el1(read_el1_ctx_the(ctx, rcwsmask_el1));
1949 }
1950
1951 if (is_feat_sctlr2_supported()) {
1952 write_sctlr2_el1(read_el1_ctx_sctlr2(ctx, sctlr2_el1));
1953 }
1954
1955 if (is_feat_ls64_accdata_supported()) {
1956 write_accdata_el1(read_el1_ctx_ls64(ctx, accdata_el1));
1957 }
1958 }
1959
1960 /*******************************************************************************
1961 * The next couple of functions are used by runtime services to save and restore
1962 * EL1 context on the 'cpu_context' structure for the specified security state.
1963 ******************************************************************************/
cm_el1_sysregs_context_save(uint32_t security_state)1964 void cm_el1_sysregs_context_save(uint32_t security_state)
1965 {
1966 cpu_context_t *ctx;
1967
1968 ctx = cm_get_context(security_state);
1969 assert(ctx != NULL);
1970
1971 el1_sysregs_context_save(get_el1_sysregs_ctx(ctx));
1972
1973 #if IMAGE_BL31
1974 if (security_state == SECURE) {
1975 PUBLISH_EVENT(cm_exited_secure_world);
1976 } else {
1977 PUBLISH_EVENT(cm_exited_normal_world);
1978 }
1979 #endif
1980 }
1981
cm_el1_sysregs_context_restore(uint32_t security_state)1982 void cm_el1_sysregs_context_restore(uint32_t security_state)
1983 {
1984 cpu_context_t *ctx;
1985
1986 ctx = cm_get_context(security_state);
1987 assert(ctx != NULL);
1988
1989 el1_sysregs_context_restore(get_el1_sysregs_ctx(ctx));
1990
1991 #if IMAGE_BL31
1992 if (security_state == SECURE) {
1993 PUBLISH_EVENT(cm_entering_secure_world);
1994 } else {
1995 PUBLISH_EVENT(cm_entering_normal_world);
1996 }
1997 #endif
1998 }
1999
2000 #endif /* ((IMAGE_BL1) || (IMAGE_BL31 && (!CTX_INCLUDE_EL2_REGS))) */
2001
2002 /*******************************************************************************
2003 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
2004 * given security state with the given entrypoint
2005 ******************************************************************************/
cm_set_elr_el3(uint32_t security_state,uintptr_t entrypoint)2006 void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
2007 {
2008 cpu_context_t *ctx;
2009 el3_state_t *state;
2010
2011 ctx = cm_get_context(security_state);
2012 assert(ctx != NULL);
2013
2014 /* Populate EL3 state so that ERET jumps to the correct entry */
2015 state = get_el3state_ctx(ctx);
2016 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
2017 }
2018
2019 /*******************************************************************************
2020 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
2021 * pertaining to the given security state
2022 ******************************************************************************/
cm_set_elr_spsr_el3(uint32_t security_state,uintptr_t entrypoint,uint32_t spsr)2023 void cm_set_elr_spsr_el3(uint32_t security_state,
2024 uintptr_t entrypoint, uint32_t spsr)
2025 {
2026 cpu_context_t *ctx;
2027 el3_state_t *state;
2028
2029 ctx = cm_get_context(security_state);
2030 assert(ctx != NULL);
2031
2032 /* Populate EL3 state so that ERET jumps to the correct entry */
2033 state = get_el3state_ctx(ctx);
2034 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
2035 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
2036 }
2037
2038 /*******************************************************************************
2039 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
2040 * pertaining to the given security state using the value and bit position
2041 * specified in the parameters. It preserves all other bits.
2042 ******************************************************************************/
cm_write_scr_el3_bit(uint32_t security_state,uint32_t bit_pos,uint32_t value)2043 void cm_write_scr_el3_bit(uint32_t security_state,
2044 uint32_t bit_pos,
2045 uint32_t value)
2046 {
2047 cpu_context_t *ctx;
2048 el3_state_t *state;
2049 u_register_t scr_el3;
2050
2051 ctx = cm_get_context(security_state);
2052 assert(ctx != NULL);
2053
2054 /* Ensure that the bit position is a valid one */
2055 assert(((1UL << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
2056
2057 /* Ensure that the 'value' is only a bit wide */
2058 assert(value <= 1U);
2059
2060 /*
2061 * Get the SCR_EL3 value from the cpu context, clear the desired bit
2062 * and set it to its new value.
2063 */
2064 state = get_el3state_ctx(ctx);
2065 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
2066 scr_el3 &= ~(1UL << bit_pos);
2067 scr_el3 |= (u_register_t)value << bit_pos;
2068 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
2069 }
2070
2071 /*******************************************************************************
2072 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
2073 * given security state.
2074 ******************************************************************************/
cm_get_scr_el3(uint32_t security_state)2075 u_register_t cm_get_scr_el3(uint32_t security_state)
2076 {
2077 const cpu_context_t *ctx;
2078 const el3_state_t *state;
2079
2080 ctx = cm_get_context(security_state);
2081 assert(ctx != NULL);
2082
2083 /* Populate EL3 state so that ERET jumps to the correct entry */
2084 state = get_el3state_ctx(ctx);
2085 return read_ctx_reg(state, CTX_SCR_EL3);
2086 }
2087
2088 /*******************************************************************************
2089 * This function is used to program the context that's used for exception
2090 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
2091 * the required security state
2092 ******************************************************************************/
cm_set_next_eret_context(uint32_t security_state)2093 void cm_set_next_eret_context(uint32_t security_state)
2094 {
2095 cpu_context_t *ctx;
2096
2097 ctx = cm_get_context(security_state);
2098 assert(ctx != NULL);
2099
2100 cm_set_next_context(ctx);
2101 }
2102