1/* 2 * Copyright (c) 2019-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v1 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635 32 /* Inserts a DMB SY before and after MRS PAR_EL1 */ 33 ldr x0, =0x0 34 msr NEOVERSE_V1_CPUPSELR_EL3, x0 35 ldr x0, = 0xEE070F14 36 msr NEOVERSE_V1_CPUPOR_EL3, x0 37 ldr x0, = 0xFFFF0FFF 38 msr NEOVERSE_V1_CPUPMR_EL3, x0 39 ldr x0, =0x4005027FF 40 msr NEOVERSE_V1_CPUPCR_EL3, x0 41 42 /* Inserts a DMB SY before STREX imm offset */ 43 ldr x0, =0x1 44 msr NEOVERSE_V1_CPUPSELR_EL3, x0 45 ldr x0, =0x00e8400000 46 msr NEOVERSE_V1_CPUPOR_EL3, x0 47 ldr x0, =0x00fff00000 48 msr NEOVERSE_V1_CPUPMR_EL3, x0 49 ldr x0, = 0x4001027FF 50 msr NEOVERSE_V1_CPUPCR_EL3, x0 51 52 /* Inserts a DMB SY before STREX[BHD}/STLEX* */ 53 ldr x0, =0x2 54 msr NEOVERSE_V1_CPUPSELR_EL3, x0 55 ldr x0, =0x00e8c00040 56 msr NEOVERSE_V1_CPUPOR_EL3, x0 57 ldr x0, =0x00fff00040 58 msr NEOVERSE_V1_CPUPMR_EL3, x0 59 ldr x0, = 0x4001027FF 60 msr NEOVERSE_V1_CPUPCR_EL3, x0 61 62 /* Inserts a DMB SY after STREX imm offset */ 63 ldr x0, =0x3 64 msr NEOVERSE_V1_CPUPSELR_EL3, x0 65 ldr x0, =0x00e8400000 66 msr NEOVERSE_V1_CPUPOR_EL3, x0 67 ldr x0, =0x00fff00000 68 msr NEOVERSE_V1_CPUPMR_EL3, x0 69 ldr x0, = 0x4004027FF 70 msr NEOVERSE_V1_CPUPCR_EL3, x0 71 72 /* Inserts a DMB SY after STREX[BHD}/STLEX* */ 73 ldr x0, =0x4 74 msr NEOVERSE_V1_CPUPSELR_EL3, x0 75 ldr x0, =0x00e8c00040 76 msr NEOVERSE_V1_CPUPOR_EL3, x0 77 ldr x0, =0x00fff00040 78 msr NEOVERSE_V1_CPUPMR_EL3, x0 79 ldr x0, = 0x4004027FF 80 msr NEOVERSE_V1_CPUPCR_EL3, x0 81 82workaround_reset_end neoverse_v1, ERRATUM(1618635) 83 84check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0) 85 86workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420 87 /* Set bit 53 in CPUECTLR_EL1 */ 88 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53 89workaround_reset_end neoverse_v1, ERRATUM(1774420) 90 91check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0) 92 93workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573 94 /* Set bit 2 in ACTLR2_EL1 */ 95 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2 96workaround_reset_end neoverse_v1, ERRATUM(1791573) 97 98check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0) 99 100workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267 101 /* Set bit 28 in ACTLR2_EL1 */ 102 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28 103workaround_reset_end neoverse_v1, ERRATUM(1852267) 104 105check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0) 106 107workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756 108 /* Set bit 8 in CPUECTLR_EL1 */ 109 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8 110workaround_reset_end neoverse_v1, ERRATUM(1925756) 111 112check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1) 113 114workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577 115 mov x0, #0 116 msr S3_6_C15_C8_0, x0 117 ldr x0, =0x10E3900002 118 msr S3_6_C15_C8_2, x0 119 ldr x0, =0x10FFF00083 120 msr S3_6_C15_C8_3, x0 121 ldr x0, =0x2001003FF 122 msr S3_6_C15_C8_1, x0 123 124 mov x0, #1 125 msr S3_6_C15_C8_0, x0 126 ldr x0, =0x10E3800082 127 msr S3_6_C15_C8_2, x0 128 ldr x0, =0x10FFF00083 129 msr S3_6_C15_C8_3, x0 130 ldr x0, =0x2001003FF 131 msr S3_6_C15_C8_1, x0 132 133 mov x0, #2 134 msr S3_6_C15_C8_0, x0 135 ldr x0, =0x10E3800200 136 msr S3_6_C15_C8_2, x0 137 ldr x0, =0x10FFF003E0 138 msr S3_6_C15_C8_3, x0 139 ldr x0, =0x2001003FF 140 msr S3_6_C15_C8_1, x0 141 142workaround_reset_end neoverse_v1, ERRATUM(1940577) 143 144check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1) 145 146workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096 147 mov x0, #0x3 148 msr S3_6_C15_C8_0, x0 149 ldr x0, =0xEE010F12 150 msr S3_6_C15_C8_2, x0 151 ldr x0, =0xFFFF0FFF 152 msr S3_6_C15_C8_3, x0 153 ldr x0, =0x80000000003FF 154 msr S3_6_C15_C8_1, x0 155workaround_reset_end neoverse_v1, ERRATUM(1966096) 156 157check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1) 158 159workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242 160 mov x0, #0x3 161 msr S3_6_C15_C8_0, x0 162 ldr x0, =0xEE720F14 163 msr S3_6_C15_C8_2, x0 164 ldr x0, =0xFFFF0FDF 165 msr S3_6_C15_C8_3, x0 166 ldr x0, =0x40000005003FF 167 msr S3_6_C15_C8_1, x0 168workaround_reset_end neoverse_v1, ERRATUM(2139242) 169 170check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1) 171 172workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392 173 ldr x0, =0x5 174 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 175 ldr x0, =0x10F600E000 176 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 177 ldr x0, =0x10FF80E000 178 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 179 ldr x0, =0x80000000003FF 180 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 181workaround_reset_end neoverse_v1, ERRATUM(2216392) 182 183check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1) 184 185workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912 186 /* Set bit 0 in ACTLR2_EL1 */ 187 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0 188workaround_reset_end neoverse_v1, ERRATUM(2294912) 189 190check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 2) 191 192workaround_reset_start neoverse_v1, ERRATUM(2348377), ERRATA_V1_2348377 193 /* Set bit 61 in CPUACTLR5_EL1 */ 194 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_61 195workaround_reset_end neoverse_v1, ERRATUM(2348377) 196 197check_erratum_ls neoverse_v1, ERRATUM(2348377), CPU_REV(1, 1) 198 199workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203 200 /* Set bit 40 in ACTLR2_EL1 */ 201 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40 202workaround_reset_end neoverse_v1, ERRATUM(2372203) 203 204check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1) 205 206workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093 207 /* dsb before isb of power down sequence */ 208 dsb sy 209workaround_runtime_end neoverse_v1, ERRATUM(2743093) 210 211check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2) 212 213workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233 214 sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56 215 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55 216workaround_reset_end neoverse_v1, ERRATUM(2743233) 217 218check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2) 219 220workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461 221 sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47 222workaround_reset_end neoverse_v1, ERRATUM(2779461) 223 224check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2) 225 226 227workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960 228#if IMAGE_BL31 229 /* 230 * The Neoverse-V1 generic vectors are overridden to apply errata 231 * mitigation on exception entry from lower ELs. 232 */ 233 override_vector_table wa_cve_vbar_neoverse_v1 234#endif /* IMAGE_BL31 */ 235workaround_reset_end neoverse_v1, CVE(2022,23960) 236 237check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 238 239/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 240workaround_reset_start neoverse_v1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 241 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, BIT(46) 242workaround_reset_end neoverse_v1, CVE(2024, 5660) 243 244check_erratum_ls neoverse_v1, CVE(2024, 5660), CPU_REV(1, 2) 245 246 /* --------------------------------------------- 247 * HW will do the cache maintenance while powering down 248 * --------------------------------------------- 249 */ 250func neoverse_v1_core_pwr_dwn 251 /* --------------------------------------------- 252 * Enable CPU power down bit in power control register 253 * --------------------------------------------- 254 */ 255 sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 256 apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093 257 258 isb 259 ret 260endfunc neoverse_v1_core_pwr_dwn 261 262cpu_reset_func_start neoverse_v1 263 /* Disable speculative loads */ 264 msr SSBS, xzr 265cpu_reset_func_end neoverse_v1 266 267 /* --------------------------------------------- 268 * This function provides Neoverse-V1 specific 269 * register information for crash reporting. 270 * It needs to return with x6 pointing to 271 * a list of register names in ascii and 272 * x8 - x15 having values of registers to be 273 * reported. 274 * --------------------------------------------- 275 */ 276.section .rodata.neoverse_v1_regs, "aS" 277neoverse_v1_regs: /* The ascii list of register names to be reported */ 278 .asciz "cpuectlr_el1", "" 279 280func neoverse_v1_cpu_reg_dump 281 adr x6, neoverse_v1_regs 282 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 283 ret 284endfunc neoverse_v1_cpu_reg_dump 285 286declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 287 neoverse_v1_reset_func, \ 288 neoverse_v1_core_pwr_dwn 289