1/* 2 * Copyright (c) 2019-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <neoverse_v1.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13#include "wa_cve_2022_23960_bhb_vector.S" 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Neoverse V1 must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue neoverse_v1 26 27#if WORKAROUND_CVE_2022_23960 28 wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1 29#endif /* WORKAROUND_CVE_2022_23960 */ 30 31workaround_reset_start neoverse_v1, ERRATUM(1542436), ERRATA_V1_1542436 32 sysreg_bit_set NEOVERSE_V1_CPUACTLR4_EL1, BIT(14) 33workaround_reset_end neoverse_v1, ERRATUM(1542436) 34 35check_erratum_ls neoverse_v1, ERRATUM(1542436), CPU_REV(0, 0) 36 37workaround_reset_start neoverse_v1, ERRATUM(1618634), ERRATA_V1_1618634 38 sysreg_bit_set NEOVERSE_V1_CPUACTLR_EL1, BIT(13) 39workaround_reset_end neoverse_v1, ERRATUM(1618634) 40 41check_erratum_ls neoverse_v1, ERRATUM(1618634), CPU_REV(0, 0) 42 43workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635 44 /* Inserts a DMB SY before and after MRS PAR_EL1 */ 45 ldr x0, =0x0 46 msr NEOVERSE_V1_CPUPSELR_EL3, x0 47 ldr x0, = 0xEE070F14 48 msr NEOVERSE_V1_CPUPOR_EL3, x0 49 ldr x0, = 0xFFFF0FFF 50 msr NEOVERSE_V1_CPUPMR_EL3, x0 51 ldr x0, =0x4005027FF 52 msr NEOVERSE_V1_CPUPCR_EL3, x0 53 54 /* Inserts a DMB SY before STREX imm offset */ 55 ldr x0, =0x1 56 msr NEOVERSE_V1_CPUPSELR_EL3, x0 57 ldr x0, =0x00e8400000 58 msr NEOVERSE_V1_CPUPOR_EL3, x0 59 ldr x0, =0x00fff00000 60 msr NEOVERSE_V1_CPUPMR_EL3, x0 61 ldr x0, = 0x4001027FF 62 msr NEOVERSE_V1_CPUPCR_EL3, x0 63 64 /* Inserts a DMB SY before STREX[BHD}/STLEX* */ 65 ldr x0, =0x2 66 msr NEOVERSE_V1_CPUPSELR_EL3, x0 67 ldr x0, =0x00e8c00040 68 msr NEOVERSE_V1_CPUPOR_EL3, x0 69 ldr x0, =0x00fff00040 70 msr NEOVERSE_V1_CPUPMR_EL3, x0 71 ldr x0, = 0x4001027FF 72 msr NEOVERSE_V1_CPUPCR_EL3, x0 73 74 /* Inserts a DMB SY after STREX imm offset */ 75 ldr x0, =0x3 76 msr NEOVERSE_V1_CPUPSELR_EL3, x0 77 ldr x0, =0x00e8400000 78 msr NEOVERSE_V1_CPUPOR_EL3, x0 79 ldr x0, =0x00fff00000 80 msr NEOVERSE_V1_CPUPMR_EL3, x0 81 ldr x0, = 0x4004027FF 82 msr NEOVERSE_V1_CPUPCR_EL3, x0 83 84 /* Inserts a DMB SY after STREX[BHD}/STLEX* */ 85 ldr x0, =0x4 86 msr NEOVERSE_V1_CPUPSELR_EL3, x0 87 ldr x0, =0x00e8c00040 88 msr NEOVERSE_V1_CPUPOR_EL3, x0 89 ldr x0, =0x00fff00040 90 msr NEOVERSE_V1_CPUPMR_EL3, x0 91 ldr x0, = 0x4004027FF 92 msr NEOVERSE_V1_CPUPCR_EL3, x0 93 94workaround_reset_end neoverse_v1, ERRATUM(1618635) 95 96check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0) 97 98workaround_reset_start neoverse_v1, ERRATUM(1618636), ERRATA_V1_1618636 99 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, BIT(8) 100workaround_reset_end neoverse_v1, ERRATUM(1618636) 101 102check_erratum_ls neoverse_v1, ERRATUM(1618636), CPU_REV(0, 0) 103 104workaround_reset_start neoverse_v1, ERRATUM(1619807), ERRATA_V1_1619807 105 sysreg_bit_set NEOVERSE_V1_CPUACTLR_EL1, BIT(11) 106workaround_reset_end neoverse_v1, ERRATUM(1619807) 107 108check_erratum_ls neoverse_v1, ERRATUM(1619807), CPU_REV(0, 0) 109 110workaround_reset_start neoverse_v1, ERRATUM(1654562), ERRATA_V1_1654562 111 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, BIT(1) 112workaround_reset_end neoverse_v1, ERRATUM(1654562) 113 114check_erratum_ls neoverse_v1, ERRATUM(1654562), CPU_REV(0, 0) 115 116workaround_reset_start neoverse_v1, ERRATUM(1674403), ERRATA_V1_1674403 117 sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, BIT(12) 118workaround_reset_end neoverse_v1, ERRATUM(1674403) 119 120check_erratum_ls neoverse_v1, ERRATUM(1674403), CPU_REV(0, 0) 121 122workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420 123 /* Set bit 53 in CPUECTLR_EL1 */ 124 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53 125workaround_reset_end neoverse_v1, ERRATUM(1774420) 126 127check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0) 128 129workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573 130 /* Set bit 2 in ACTLR2_EL1 */ 131 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2 132workaround_reset_end neoverse_v1, ERRATUM(1791573) 133 134check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0) 135 136workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267 137 /* Set bit 28 in ACTLR2_EL1 */ 138 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28 139workaround_reset_end neoverse_v1, ERRATUM(1852267) 140 141check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0) 142 143workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756 144 /* Set bit 8 in CPUECTLR_EL1 */ 145 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8 146workaround_reset_end neoverse_v1, ERRATUM(1925756) 147 148check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1) 149 150workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577 151 mov x0, #0 152 msr S3_6_C15_C8_0, x0 153 ldr x0, =0x10E3900002 154 msr S3_6_C15_C8_2, x0 155 ldr x0, =0x10FFF00083 156 msr S3_6_C15_C8_3, x0 157 ldr x0, =0x2001003FF 158 msr S3_6_C15_C8_1, x0 159 160 mov x0, #1 161 msr S3_6_C15_C8_0, x0 162 ldr x0, =0x10E3800082 163 msr S3_6_C15_C8_2, x0 164 ldr x0, =0x10FFF00083 165 msr S3_6_C15_C8_3, x0 166 ldr x0, =0x2001003FF 167 msr S3_6_C15_C8_1, x0 168 169 mov x0, #2 170 msr S3_6_C15_C8_0, x0 171 ldr x0, =0x10E3800200 172 msr S3_6_C15_C8_2, x0 173 ldr x0, =0x10FFF003E0 174 msr S3_6_C15_C8_3, x0 175 ldr x0, =0x2001003FF 176 msr S3_6_C15_C8_1, x0 177 178workaround_reset_end neoverse_v1, ERRATUM(1940577) 179 180check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1) 181 182workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096 183 mov x0, #0x3 184 msr S3_6_C15_C8_0, x0 185 ldr x0, =0xEE010F12 186 msr S3_6_C15_C8_2, x0 187 ldr x0, =0xFFFF0FFF 188 msr S3_6_C15_C8_3, x0 189 ldr x0, =0x80000000003FF 190 msr S3_6_C15_C8_1, x0 191workaround_reset_end neoverse_v1, ERRATUM(1966096) 192 193check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1) 194 195workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242 196 mov x0, #0x3 197 msr S3_6_C15_C8_0, x0 198 ldr x0, =0xEE720F14 199 msr S3_6_C15_C8_2, x0 200 ldr x0, =0xFFFF0FDF 201 msr S3_6_C15_C8_3, x0 202 ldr x0, =0x40000005003FF 203 msr S3_6_C15_C8_1, x0 204workaround_reset_end neoverse_v1, ERRATUM(2139242) 205 206check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1) 207 208workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392 209 ldr x0, =0x5 210 msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ 211 ldr x0, =0x10F600E000 212 msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ 213 ldr x0, =0x10FF80E000 214 msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ 215 ldr x0, =0x80000000003FF 216 msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ 217workaround_reset_end neoverse_v1, ERRATUM(2216392) 218 219check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1) 220 221workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912 222 /* Set bit 0 in ACTLR2_EL1 */ 223 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0 224workaround_reset_end neoverse_v1, ERRATUM(2294912) 225 226check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 2) 227 228workaround_reset_start neoverse_v1, ERRATUM(2348377), ERRATA_V1_2348377 229 /* Set bit 61 in CPUACTLR5_EL1 */ 230 sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_61 231workaround_reset_end neoverse_v1, ERRATUM(2348377) 232 233check_erratum_ls neoverse_v1, ERRATUM(2348377), CPU_REV(1, 1) 234 235workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203 236 /* Set bit 40 in ACTLR2_EL1 */ 237 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40 238workaround_reset_end neoverse_v1, ERRATUM(2372203) 239 240check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1) 241 242workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093 243 /* dsb before isb of power down sequence */ 244 dsb sy 245workaround_runtime_end neoverse_v1, ERRATUM(2743093) 246 247check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2) 248 249workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233 250 sysreg_lazy_start NEOVERSE_V1_ACTLR5_EL1 251 sysreg_lazy_clear NEOVERSE_V1_ACTLR5_EL1_BIT_56 252 sysreg_lazy_set NEOVERSE_V1_ACTLR5_EL1_BIT_55 253 sysreg_lazy_commit NEOVERSE_V1_ACTLR5_EL1 254workaround_reset_end neoverse_v1, ERRATUM(2743233) 255 256check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2) 257 258workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461 259 sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47 260workaround_reset_end neoverse_v1, ERRATUM(2779461) 261 262check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2) 263 264workaround_reset_start neoverse_v1, ERRATUM(3888016), ERRATA_V1_3888016 265 sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, BIT(22) 266workaround_reset_end neoverse_v1, ERRATUM(3888016) 267 268check_erratum_chosen neoverse_v1, ERRATUM(3888016), ERRATA_V1_3888016 269 270workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960 271#if IMAGE_BL31 272 /* 273 * The Neoverse-V1 generic vectors are overridden to apply errata 274 * mitigation on exception entry from lower ELs. 275 */ 276 override_vector_table wa_cve_vbar_neoverse_v1 277#endif /* IMAGE_BL31 */ 278workaround_reset_end neoverse_v1, CVE(2022,23960) 279 280check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 281 282/* Disable hardware page aggregation. Enables mitigation for `CVE-2024-5660` */ 283workaround_reset_start neoverse_v1, CVE(2024, 5660), WORKAROUND_CVE_2024_5660 284 sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, BIT(46) 285workaround_reset_end neoverse_v1, CVE(2024, 5660) 286 287check_erratum_ls neoverse_v1, CVE(2024, 5660), CPU_REV(1, 2) 288 289 /* --------------------------------------------- 290 * HW will do the cache maintenance while powering down 291 * --------------------------------------------- 292 */ 293func neoverse_v1_core_pwr_dwn 294 /* --------------------------------------------- 295 * Enable CPU power down bit in power control register 296 * --------------------------------------------- 297 */ 298 sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 299 apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093 300 301 isb 302 ret 303endfunc neoverse_v1_core_pwr_dwn 304 305cpu_reset_func_start neoverse_v1 306 /* Disable speculative loads */ 307 msr SSBS, xzr 308cpu_reset_func_end neoverse_v1 309 310 /* --------------------------------------------- 311 * This function provides Neoverse-V1 specific 312 * register information for crash reporting. 313 * It needs to return with x6 pointing to 314 * a list of register names in ascii and 315 * x8 - x15 having values of registers to be 316 * reported. 317 * --------------------------------------------- 318 */ 319.section .rodata.neoverse_v1_regs, "aS" 320neoverse_v1_regs: /* The ascii list of register names to be reported */ 321 .asciz "cpuectlr_el1", "" 322 323func neoverse_v1_cpu_reg_dump 324 adr x6, neoverse_v1_regs 325 mrs x8, NEOVERSE_V1_CPUECTLR_EL1 326 ret 327endfunc neoverse_v1_cpu_reg_dump 328 329declare_cpu_ops neoverse_v1, NEOVERSE_V1_MIDR, \ 330 neoverse_v1_reset_func, \ 331 neoverse_v1_core_pwr_dwn 332