1/* 2 * Copyright (c) 2025-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <lsc25_p_core.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "LSC25 P-core must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "LSC25 P-core supports only AArch64. Compile with " \ 22 "CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue lsc25_p_core 26 27cpu_reset_func_start lsc25_p_core 28 /* ---------------------------------------------------- 29 * Disable speculative loads 30 * ---------------------------------------------------- 31 */ 32 msr SSBS, xzr 33 enable_mpmm 34cpu_reset_func_end lsc25_p_core 35 36func lsc25_p_core_core_pwr_dwn 37 /* 38 * When software running at lower ELs requests power down without first 39 * disabling SME, the CME connected to it will reject its power down 40 * request. Skip setting the PWRDN_EN bit, downgrading the powerdown 41 * request to a simple WFI wait, to get a minimal amount of power saving 42 * rather than an instant pabandon. 43 */ 44 mrs x0, SVCR 45 cbnz x0, lsc25_p_core_skip_pwr_dwn 46 47 /* --------------------------------------------------- 48 * Flip CPU power down bit in power control register. 49 * It will be set on powerdown and cleared on wakeup 50 * --------------------------------------------------- 51 */ 52 sysreg_bit_toggle LSC25_P_CORE_IMP_CPUPWRCTLR_EL1, \ 53 LSC25_P_CORE_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 54 isb 55lsc25_p_core_skip_pwr_dwn: 56 signal_pabandon_handled 57 ret 58endfunc lsc25_p_core_core_pwr_dwn 59 60.section .rodata.lsc25_p_core_regs, "aS" 61lsc25_p_core_regs: /* The ASCII list of register names to be reported */ 62 .asciz "cpuectlr_el1", "" 63 64func lsc25_p_core_cpu_reg_dump 65 adr x6, lsc25_p_core_regs 66 mrs x8, LSC25_P_CORE_IMP_CPUECTLR_EL1 67 ret 68endfunc lsc25_p_core_cpu_reg_dump 69 70declare_cpu_ops lsc25_p_core, LSC25_P_CORE_MIDR, \ 71 lsc25_p_core_reset_func, \ 72 lsc25_p_core_core_pwr_dwn 73