1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <lsc25_p_core.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "LSC25 P-core must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "LSC25 P-core supports only AArch64. Compile with " \ 22 "CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25#if ERRATA_SME_POWER_DOWN == 0 26#error "LSC25 P-core needs ERRATA_SME_POWER_DOWN=1 to powerdown correctly" 27#endif 28 29cpu_reset_prologue lsc25_p_core 30 31cpu_reset_func_start lsc25_p_core 32 /* ---------------------------------------------------- 33 * Disable speculative loads 34 * ---------------------------------------------------- 35 */ 36 msr SSBS, xzr 37 enable_mpmm 38cpu_reset_func_end lsc25_p_core 39 40func lsc25_p_core_core_pwr_dwn 41 /* --------------------------------------------------- 42 * Flip CPU power down bit in power control register. 43 * It will be set on powerdown and cleared on wakeup 44 * --------------------------------------------------- 45 */ 46 sysreg_bit_toggle LSC25_P_CORE_IMP_CPUPWRCTLR_EL1, \ 47 LSC25_P_CORE_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 48 isb 49 signal_pabandon_handled 50 ret 51endfunc lsc25_p_core_core_pwr_dwn 52 53.section .rodata.lsc25_p_core_regs, "aS" 54lsc25_p_core_regs: /* The ASCII list of register names to be reported */ 55 .asciz "cpuectlr_el1", "" 56 57func lsc25_p_core_cpu_reg_dump 58 adr x6, lsc25_p_core_regs 59 mrs x8, LSC25_P_CORE_IMP_CPUECTLR_EL1 60 ret 61endfunc lsc25_p_core_cpu_reg_dump 62 63declare_cpu_ops lsc25_p_core, LSC25_P_CORE_MIDR, \ 64 lsc25_p_core_reset_func, \ 65 lsc25_p_core_core_pwr_dwn 66