1/* 2 * Copyright (c) 2025-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <lsc25_e_core.h> 11#include <cpu_macros.S> 12#include <plat_macros.S> 13 14/* Hardware handled coherency */ 15#if HW_ASSISTED_COHERENCY == 0 16#error "LSC25 E-core must be compiled with HW_ASSISTED_COHERENCY enabled" 17#endif 18 19/* 64-bit only core */ 20#if CTX_INCLUDE_AARCH32_REGS == 1 21#error "LSC25 E-core supports only AArch64. Compile with " \ 22 "CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue lsc25_e_core 26 27cpu_reset_func_start lsc25_e_core 28 /* ---------------------------------------------------- 29 * Disable speculative loads 30 * ---------------------------------------------------- 31 */ 32 msr SSBS, xzr 33 enable_mpmm 34cpu_reset_func_end lsc25_e_core 35 36 /* ---------------------------------------------------- 37 * HW will do the cache maintenance while powering down 38 * ---------------------------------------------------- 39 */ 40func lsc25_e_core_core_pwr_dwn 41 /* 42 * When software running at lower ELs requests power down without first 43 * disabling SME, the CME connected to it will reject its power down 44 * request. Skip setting the PWRDN_EN bit, downgrading the powerdown 45 * request to a simple WFI wait, to get a minimal amount of power saving 46 * rather than an instant pabandon. 47 */ 48 mrs x0, SVCR 49 cbnz x0, lsc25_e_core_skip_pwr_dwn 50 51 /* --------------------------------------------------- 52 * Flip CPU power down bit in power control register. 53 * It will be set on powerdown and cleared on wakeup 54 * --------------------------------------------------- 55 */ 56 sysreg_bit_toggle LSC25_E_CORE_IMP_CPUPWRCTLR_EL1, \ 57 LSC25_E_CORE_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 58 isb 59lsc25_e_core_skip_pwr_dwn: 60 signal_pabandon_handled 61 ret 62endfunc lsc25_e_core_core_pwr_dwn 63 64 /* --------------------------------------------- 65 * This function provides LSC25 E-Core specific 66 * register information for crash reporting. 67 * It needs to return with x6 pointing to 68 * a list of register names in ascii and 69 * x8 - x15 having values of registers to be 70 * reported. 71 * --------------------------------------------- 72 */ 73.section .rodata.lsc25_e_core_regs, "aS" 74lsc25_e_core_regs: /* The ASCII list of register names to be reported */ 75 .asciz "imp_cpuectlr_el1", "" 76 77func lsc25_e_core_cpu_reg_dump 78 adr x6, lsc25_e_core_regs 79 mrs x8, LSC25_E_CORE_IMP_CPUECTLR_EL1 80 ret 81endfunc lsc25_e_core_cpu_reg_dump 82 83declare_cpu_ops lsc25_e_core, LSC25_E_CORE_MIDR, \ 84 lsc25_e_core_reset_func, \ 85 lsc25_e_core_core_pwr_dwn 86