1/* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <common/bl_common.h> 10#include <cortex_a720.h> 11#include <cpu_macros.S> 12#include <dsu_macros.S> 13#include <plat_macros.S> 14#include "wa_cve_2022_23960_bhb_vector.S" 15 16/* Hardware handled coherency */ 17#if HW_ASSISTED_COHERENCY == 0 18#error "Cortex A720 must be compiled with HW_ASSISTED_COHERENCY enabled" 19#endif 20 21/* 64-bit only core */ 22#if CTX_INCLUDE_AARCH32_REGS == 1 23#error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 24#endif 25 26cpu_reset_prologue cortex_a720 27 28.global check_erratum_cortex_a720_3699561 29 30workaround_reset_start cortex_a720, ERRATUM(2729604), ERRATA_A720_2729604 31 sysreg_bit_set CORTEX_A720_CPUACTLR_EL1, (BIT(60) | BIT(61)) 32workaround_reset_end cortex_a720, ERRATUM(2729604) 33 34check_erratum_ls cortex_a720, ERRATUM(2729604), CPU_REV(0, 1) 35 36workaround_reset_start cortex_a720, ERRATUM(2792132), ERRATA_A720_2792132 37 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(26) 38workaround_reset_end cortex_a720, ERRATUM(2792132) 39 40check_erratum_ls cortex_a720, ERRATUM(2792132), CPU_REV(0, 1) 41 42workaround_reset_start cortex_a720, ERRATUM(2844092), ERRATA_A720_2844092 43 sysreg_bit_set CORTEX_A720_CPUACTLR4_EL1, BIT(11) 44workaround_reset_end cortex_a720, ERRATUM(2844092) 45 46check_erratum_ls cortex_a720, ERRATUM(2844092), CPU_REV(0, 1) 47 48workaround_reset_start cortex_a720, ERRATUM(2900952), ERRATA_DSU_2900952 49 errata_dsu_2900952_wa_apply 50workaround_reset_end cortex_a720, ERRATUM(2900952) 51 52check_erratum_custom_start cortex_a720, ERRATUM(2900952) 53 check_errata_dsu_2900952_applies 54 ret 55check_erratum_custom_end cortex_a720, ERRATUM(2900952) 56 57workaround_reset_start cortex_a720, ERRATUM(2926083), ERRATA_A720_2926083 58/* Erratum 2926083 workaround is required only if SPE is enabled */ 59#if ENABLE_SPE_FOR_NS != 0 60 /* Check if Static profiling extension is implemented or present. */ 61 mrs x1, id_aa64dfr0_el1 62 ubfx x0, x1, ID_AA64DFR0_PMS_SHIFT, #4 63 cbz x0, 1f 64 /* Apply the workaround by setting CPUACTLR_EL1[58:57] = 0b11. */ 65 sysreg_lazy_start CORTEX_A720_CPUACTLR_EL1 66 sysreg_lazy_set BIT(57) 67 sysreg_lazy_set BIT(58) 68 sysreg_lazy_commit CORTEX_A720_CPUACTLR_EL1 691: 70#endif 71workaround_reset_end cortex_a720, ERRATUM(2926083) 72 73check_erratum_ls cortex_a720, ERRATUM(2926083), CPU_REV(0, 1) 74 75workaround_reset_start cortex_a720, ERRATUM(2940794), ERRATA_A720_2940794 76 sysreg_bit_set CORTEX_A720_CPUACTLR2_EL1, BIT(37) 77workaround_reset_end cortex_a720, ERRATUM(2940794) 78 79check_erratum_ls cortex_a720, ERRATUM(2940794), CPU_REV(0, 1) 80 81workaround_runtime_start cortex_a720, ERRATUM(3456091), ERRATA_A720_3456091 82 speculation_barrier 83workaround_runtime_end cortex_a720, ERRATUM(3456091) 84 85check_erratum_ls cortex_a720, ERRATUM(3456091), CPU_REV(0, 2) 86 87add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561 88 89check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2) 90 91workaround_reset_start cortex_a720, ERRATUM(3711910), ERRATA_A720_3711910 92 mov x0, #5 93 msr CORTEX_A720_CPUPSELR_EL3, x0 94 ldr x0, =0xD503329F 95 msr CORTEX_A720_CPUPOR_EL3, x0 96 ldr x0, =0xFFFFF3FF 97 msr CORTEX_A720_CPUPMR_EL3, x0 98 ldr x0, =0x1004003F1 99 msr CORTEX_A720_CPUPCR_EL3, x0 100workaround_reset_end cortex_a720, ERRATUM(3711910) 101 102check_erratum_ls cortex_a720, ERRATUM(3711910), CPU_REV(0, 2) 103 104cpu_reset_func_start cortex_a720 105 /* Disable speculative loads */ 106 msr SSBS, xzr 107 apply_erratum cortex_a720, ERRATUM(3456091), ERRATA_A720_3456091 108 109 enable_mpmm 110cpu_reset_func_end cortex_a720 111 112 /* ---------------------------------------------------- 113 * HW will do the cache maintenance while powering down 114 * ---------------------------------------------------- 115 */ 116func cortex_a720_core_pwr_dwn 117 /* --------------------------------------------------- 118 * Enable CPU power down bit in power control register 119 * --------------------------------------------------- 120 */ 121 sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 122 123 isb 124 ret 125endfunc cortex_a720_core_pwr_dwn 126 127 /* --------------------------------------------- 128 * This function provides Cortex A720-specific 129 * register information for crash reporting. 130 * It needs to return with x6 pointing to 131 * a list of register names in ascii and 132 * x8 - x15 having values of registers to be 133 * reported. 134 * --------------------------------------------- 135 */ 136.section .rodata.cortex_a720_regs, "aS" 137cortex_a720_regs: /* The ascii list of register names to be reported */ 138 .asciz "cpuectlr_el1", "" 139 140func cortex_a720_cpu_reg_dump 141 adr x6, cortex_a720_regs 142 mrs x8, CORTEX_A720_CPUECTLR_EL1 143 ret 144endfunc cortex_a720_cpu_reg_dump 145 146declare_cpu_ops cortex_a720, CORTEX_A720_MIDR, \ 147 cortex_a720_reset_func, \ 148 cortex_a720_core_pwr_dwn 149