1/* 2 * Copyright (c) 2023-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_pro.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Pro must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Pro supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue c1_pro 26 27workaround_runtime_start c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 28 speculation_barrier 29workaround_runtime_end c1_pro, ERRATUM(3338470) 30 31check_erratum_ls c1_pro, ERRATUM(3338470), CPU_REV(0, 0) 32 33workaround_reset_start c1_pro, ERRATUM(3362007), ERRATA_C1PRO_3362007 34 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(27) 35workaround_reset_end c1_pro, ERRATUM(3362007) 36 37check_erratum_ls c1_pro, ERRATUM(3362007), CPU_REV(0, 0) 38 39workaround_reset_start c1_pro, ERRATUM(3619847), ERRATA_C1PRO_3619847 40 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(42) 41workaround_reset_end c1_pro, ERRATUM(3619847) 42 43check_erratum_ls c1_pro, ERRATUM(3619847), CPU_REV(0, 0) 44 45workaround_runtime_start c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 46#if ENABLE_SME_FOR_NS 47#if ENABLE_SME_FOR_NS == 2 48 is_feat_sme_present_asm x1 49 beq 1f 50#endif 51 52 sysreg_bit_set C1_PRO_IMP_CPUECTLR_EL1, BIT(57) 53 dsb sy 54 551: 56#endif 57workaround_runtime_end c1_pro, ERRATUM(3686597) 58 59check_erratum_ls c1_pro, ERRATUM(3686597), CPU_REV(1, 0) 60 61workaround_reset_start c1_pro, ERRATUM(3694158), ERRATA_C1PRO_3694158 62 mov x0, #5 63 msr C1_PRO_IMP_CPUPSELR_EL3, x0 64 isb 65 ldr x0, =0xd503329f 66 msr C1_PRO_IMP_CPUPOR_EL3, x0 67 ldr x0, =0xfffff3ff 68 msr C1_PRO_IMP_CPUPMR_EL3, x0 69 mov x1, #0 70 orr x1, x1, #1<<0 71 orr x1, x1, #3<<4 72 orr x1, x1, #0xf<<6 73 orr x1, x1, #1<<22 74 orr x1, x1, #1<<32 75 msr C1_PRO_IMP_CPUPCR_EL3, x1 76workaround_reset_end c1_pro, ERRATUM(3694158) 77 78check_erratum_ls c1_pro, ERRATUM(3694158), CPU_REV(1, 1) 79 80workaround_reset_start c1_pro, ERRATUM(3706576), ERRATA_C1PRO_3706576 81 sysreg_bit_set C1_PRO_IMP_CPUACTLR2_EL1, BIT(37) 82workaround_reset_end c1_pro, ERRATUM(3706576) 83 84check_erratum_ls c1_pro, ERRATUM(3706576), CPU_REV(1, 0) 85 86add_erratum_entry c1_pro, ERRATUM(3300099), ERRATA_C1PRO_3300099 87.global check_erratum_c1_pro_3300099 88check_erratum_ls c1_pro, ERRATUM(3300099), CPU_REV(1, 0) 89 90 /* ----------------------------------------------------------- 91 * CVE-2024-7881 is mitigated for C1-Pro using erratum 3684268 92 * workaround by disabling the affected prefetcher 93 * via IMP_CPUECTLR_EL1[49]. 94 * ----------------------------------------------------------- 95 */ 96workaround_reset_start c1_pro, CVE(2024, 7881), WORKAROUND_CVE_2024_7881 97 sysreg_bit_set C1_PRO_IMP_CPUECTLR2_EL1, BIT(49) 98 dsb sy 99workaround_reset_end c1_pro, CVE(2024, 7881) 100 101check_erratum_ls c1_pro, CVE(2024, 7881), CPU_REV(1, 0) 102 103cpu_reset_func_start c1_pro 104 /* ---------------------------------------------------- 105 * Disable speculative loads 106 * ---------------------------------------------------- 107 */ 108 msr SSBS, xzr 109 apply_erratum c1_pro, ERRATUM(3338470), ERRATA_C1PRO_3338470 110 /* model bug: not cleared on reset */ 111 sysreg_bit_clear C1_PRO_IMP_CPUPWRCTLR_EL1, \ 112 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 113 enable_mpmm 114cpu_reset_func_end c1_pro 115 116 /* ---------------------------------------------------- 117 * HW will do the cache maintenance while powering down 118 * ---------------------------------------------------- 119 */ 120func c1_pro_core_pwr_dwn 121 /* 122 * When software running at lower ELs requests power down without first 123 * disabling SME, the CME connected to it will reject its power down 124 * request. Skip setting the PWRDN_EN bit, downgrading the powerdown 125 * request to a simple WFI wait, to get a minimal amount of power saving 126 * rather than an instant pabandon. 127 */ 128#if ENABLE_SME_FOR_NS 129#if ENABLE_SME_FOR_NS == 2 130 is_feat_sme_present_asm x1 131 beq 1f 132#endif 133 mrs x0, SVCR 134 cbnz x0, c1_pro_skip_pwr_dwn 1351: 136#endif 137 138 /* --------------------------------------------------- 139 * Flip CPU power down bit in power control register. 140 * It will be set on powerdown and cleared on wakeup 141 * --------------------------------------------------- 142 */ 143 apply_erratum c1_pro, ERRATUM(3686597), ERRATA_C1PRO_3686597 144 sysreg_bit_toggle C1_PRO_IMP_CPUPWRCTLR_EL1, \ 145 C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT 146 isb 147c1_pro_skip_pwr_dwn: 148 signal_pabandon_handled 149 ret 150endfunc c1_pro_core_pwr_dwn 151 152 /* --------------------------------------------- 153 * This function provides Arm C1-Pro specific 154 * register information for crash reporting. 155 * It needs to return with x6 pointing to 156 * a list of register names in ascii and 157 * x8 - x15 having values of registers to be 158 * reported. 159 * --------------------------------------------- 160 */ 161.section .rodata.c1_pro_regs, "aS" 162c1_pro_regs: /* The ASCII list of register names to be reported */ 163 .asciz "imp_cpuectlr_el1", "" 164 165func c1_pro_cpu_reg_dump 166 adr x6, c1_pro_regs 167 mrs x8, C1_PRO_IMP_CPUECTLR_EL1 168 ret 169endfunc c1_pro_cpu_reg_dump 170 171declare_cpu_ops c1_pro, C1_PRO_MIDR, \ 172 c1_pro_reset_func, \ 173 c1_pro_core_pwr_dwn 174