1/* 2 * Copyright (c) 2023-2026, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <c1_nano.h> 10#include <common/bl_common.h> 11#include <cpu_macros.S> 12 13#include <plat_macros.S> 14 15/* Hardware handled coherency */ 16#if HW_ASSISTED_COHERENCY == 0 17#error "Arm C1-Nano must be compiled with HW_ASSISTED_COHERENCY enabled" 18#endif 19 20/* 64-bit only core */ 21#if CTX_INCLUDE_AARCH32_REGS == 1 22#error "Arm C1-Nano supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" 23#endif 24 25cpu_reset_prologue c1_nano 26 27workaround_reset_start c1_nano, ERRATUM(3392149), ERRATA_C1NANO_3392149 28 sysreg_bit_set C1_NANO_IMP_CPUACTLR3_EL1, BIT(39) 29workaround_reset_end c1_nano, ERRATUM(3392149) 30 31check_erratum_ls c1_nano, ERRATUM(3392149), CPU_REV(0, 0) 32 33workaround_reset_start c1_nano, ERRATUM(3419531), ERRATA_C1NANO_3419531 34 sysreg_bit_set C1_NANO_IMP_CPUACTLR_EL1, BIT(27) 35workaround_reset_end c1_nano, ERRATUM(3419531) 36 37check_erratum_ls c1_nano, ERRATUM(3419531), CPU_REV(0, 0) 38 39workaround_reset_start c1_nano, ERRATUM(3437202), ERRATA_C1NANO_3437202 40 sysreg_bit_set C1_NANO_IMP_CPUACTLR_EL1, BIT(26) 41workaround_reset_end c1_nano, ERRATUM(3437202) 42 43check_erratum_ls c1_nano, ERRATUM(3437202), CPU_REV(0, 0) 44 45workaround_reset_start c1_nano, ERRATUM(3516455), ERRATA_C1NANO_3516455 46#if ENABLE_SME_FOR_NS 47#if ENABLE_SME_FOR_NS == 2 48 is_feat_sme_present_asm x1 49 beq 1f 50#endif 51 52 mov x0, #0 53 msr C1_NANO_IMP_CPUPSELR_EL3, x0 54 isb 55 ldr x0, =0xA0008000 56 msr C1_NANO_IMP_CPUPOR_EL3, x0 57 ldr x0, =0xFE808000 58 msr C1_NANO_IMP_CPUPMR_EL3, x0 59 ldr x0, =0x7F9 60 movk x0, #0x20, LSL #32 61 msr C1_NANO_IMP_CPUPCR_EL3, x0 62 isb 63 mov x0, #1 64 msr C1_NANO_IMP_CPUPSELR_EL3, x0 65 isb 66 ldr x0, =0xA4604000 67 msr C1_NANO_IMP_CPUPOR_EL3, x0 68 ldr x0, =0xBE604000 69 msr C1_NANO_IMP_CPUPMR_EL3, x0 70 ldr x0, =0x7F9 71 movk x0, #0x20, LSL #32 72 msr C1_NANO_IMP_CPUPCR_EL3, x0 73 74 1: 75#endif 76workaround_reset_end c1_nano, ERRATUM(3516455) 77 78check_erratum_ls c1_nano, ERRATUM(3516455), CPU_REV(0, 0) 79 80workaround_reset_start c1_nano, ERRATUM(3616450), ERRATA_C1NANO_3616450 81#if ENABLE_SME_FOR_NS 82#if ENABLE_SME_FOR_NS == 2 83 is_feat_sme_present_asm x1 84 beq 1f 85#endif 86 87 sysreg_bit_set C1_NANO_IMP_CPUACTLR_EL1, BIT(29) 88 89 1: 90#endif 91workaround_reset_end c1_nano, ERRATUM(3616450) 92 93check_erratum_ls c1_nano, ERRATUM(3616450), CPU_REV(0, 0) 94 95workaround_reset_start c1_nano, ERRATUM(3630925), ERRATA_C1NANO_3630925 96 sysreg_bitfield_insert C1_NANO_IMP_CPUPWRCTLR_EL1, \ 97 C1_NANO_IMP_CPUPWRCTLR_EL1_WFE_RET_CTRL_BIT, \ 98 C1_NANO_IMP_CPUPWRCTLR_EL1_WFE_RET_CTRL_SHIFT, \ 99 C1_NANO_IMP_CPUPWRCTLR_EL1_WFE_RET_CTRL_WIDTH 100 101 sysreg_bitfield_insert C1_NANO_IMP_CPUPWRCTLR_EL1, \ 102 C1_NANO_IMP_CPUPWRCTLR_EL1_WFI_RET_CTRL_BIT, \ 103 C1_NANO_IMP_CPUPWRCTLR_EL1_WFI_RET_CTRL_SHIFT, \ 104 C1_NANO_IMP_CPUPWRCTLR_EL1_WFI_RET_CTRL_WIDTH 105workaround_reset_end c1_nano, ERRATUM(3630925) 106 107check_erratum_ls c1_nano, ERRATUM(3630925), CPU_REV(0, 0) 108 109workaround_runtime_start c1_nano, ERRATUM(3754876), ERRATA_C1NANO_3754876 110 tsb_csync 111workaround_runtime_end c1_nano, ERRATUM(3754876) 112 113check_erratum_ls c1_nano, ERRATUM(3754876), CPU_REV(0, 1) 114 115cpu_reset_func_start c1_nano 116 /* ---------------------------------------------------- 117 * Disable speculative loads 118 * ---------------------------------------------------- 119 */ 120 msr SSBS, xzr 121 /* model bug: not cleared on reset */ 122 sysreg_bit_clear C1_NANO_IMP_CPUPWRCTLR_EL1, \ 123 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 124 enable_mpmm 125cpu_reset_func_end c1_nano 126 127func c1_nano_core_pwr_dwn 128 /* 129 * When software running at lower ELs requests power down without first 130 * disabling SME, the CME connected to it will reject its power down 131 * request. Skip setting the PWRDN_EN bit, downgrading the powerdown 132 * request to a simple WFI wait, to get a minimal amount of power saving 133 * rather than an instant pabandon. 134 */ 135#if ENABLE_SME_FOR_NS 136#if ENABLE_SME_FOR_NS == 2 137 is_feat_sme_present_asm x1 138 beq 1f 139#endif 140 mrs x0, SVCR 141 cbnz x0, c1_nano_skip_pwr_dwn 1421: 143#endif 144 145 /* --------------------------------------------------- 146 * Enable CPU power down bit in power control register 147 * --------------------------------------------------- 148 */ 149 sysreg_bit_toggle C1_NANO_IMP_CPUPWRCTLR_EL1, \ 150 C1_NANO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT 151 isb 152 apply_erratum c1_nano, ERRATUM(3754876), ERRATA_C1NANO_3754876 153c1_nano_skip_pwr_dwn: 154 signal_pabandon_handled 155 ret 156endfunc c1_nano_core_pwr_dwn 157 158.section .rodata.c1_nano_regs, "aS" 159c1_nano_regs: /* The ASCII list of register names to be reported */ 160 .asciz "cpuectlr_el1", "" 161 162func c1_nano_cpu_reg_dump 163 adr x6, c1_nano_regs 164 mrs x8, C1_NANO_IMP_CPUECTLR_EL1 165 ret 166endfunc c1_nano_cpu_reg_dump 167 168declare_cpu_ops c1_nano, C1_NANO_MIDR, \ 169 c1_nano_reset_func, \ 170 c1_nano_core_pwr_dwn 171