1// SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause 2/* 3 * ARM Ltd. Fast Models 4 * 5 * Architecture Envelope Model (AEM) ARMv8-A 6 * ARMAEMv8AMPCT 7 * 8 * RTSM_VE_AEMv8A.lisa 9 * 10 * Copyright (c) 2017-2025, ARM Limited and Contributors. All rights reserved. 11 */ 12 13#include "rtsm_ve-motherboard.dtsi" 14 15/ { 16 model = "FVP Base"; 17 compatible = "arm,fvp-base", "arm,vexpress"; 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { 23 stdout-path = "serial0:115200n8"; 24 bootargs = "console=ttyAMA0 earlycon=pl011,0x1c090000 root=/dev/vda ip=on"; 25 }; 26 27 aliases { 28 serial0 = &v2m_serial0; 29 serial1 = &v2m_serial1; 30 serial2 = &v2m_serial2; 31 serial3 = &v2m_serial3; 32 }; 33 34 psci { 35 compatible = "arm,psci-1.0", "arm,psci-0.2"; 36 method = "smc"; 37 max-pwr-lvl = <2>; 38 }; 39 40 cpus { 41 #address-cells = <2>; 42 #size-cells = <0>; 43 44 CPU_MAP 45 46 idle-states { 47 entry-method = "psci"; 48 49 CPU_SLEEP_0: cpu-sleep-0 { 50 compatible = "arm,idle-state"; 51 local-timer-stop; 52 arm,psci-suspend-param = <0x0010000>; 53 entry-latency-us = <40>; 54 exit-latency-us = <100>; 55 min-residency-us = <150>; 56 }; 57 58 CLUSTER_SLEEP_0: cluster-sleep-0 { 59 compatible = "arm,idle-state"; 60 local-timer-stop; 61 arm,psci-suspend-param = <0x1010000>; 62 entry-latency-us = <500>; 63 exit-latency-us = <1000>; 64 min-residency-us = <2500>; 65 }; 66 }; 67 68 CPUS 69 70 L2_0: l2-cache0 { 71 compatible = "cache"; 72 }; 73 }; 74 75 memory@80000000 { 76 device_type = "memory"; 77#if (ENABLE_RME == 1) 78 reg = <0x00000000 0x80000000 0 0x7C000000>, 79 <0x00000008 0x80000000 0 0x80000000>; 80#else 81 reg = <0x00000000 0x80000000 0 0x7F000000>, 82 <0x00000008 0x80000000 0 0x80000000>; 83#endif 84 }; 85 86 reserved-memory { 87 #address-cells = <2>; 88 #size-cells = <2>; 89 ranges; 90 91 /* Chipselect 2,00000000 is physically at 0x18000000 */ 92 vram: vram@18000000 { 93 /* 8 MB of designated video RAM */ 94 compatible = "shared-dma-pool"; 95 reg = <0x00000000 0x18000000 0 0x00800000>; 96 no-map; 97 }; 98 }; 99 100 timer { 101 compatible = "arm,armv8-timer"; 102 clock-frequency = <100000000>; 103 }; 104 105 timer@2a810000 { 106 compatible = "arm,armv7-timer-mem"; 107 reg = <0x0 0x2a810000 0x0 0x10000>; 108 clock-frequency = <100000000>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0x0 0x0 0x2a810000 0x100000>; 112 113 frame@2a830000 { 114 frame-number = <1>; 115 interrupt-parent = <&gic>; 116 reg = <0x20000 0x10000>; 117 }; 118 }; 119 120 pmu { 121 compatible = "arm,armv8-pmuv3"; 122 }; 123 124 panel { 125 compatible = "arm,rtsm-display"; 126 port { 127 panel_in: endpoint { 128 remote-endpoint = <&clcd_pads>; 129 }; 130 }; 131 }; 132 133 bus@8000000 { 134 #interrupt-cells = <1>; 135 interrupt-map-mask = <0 0 63>; 136 }; 137 138#if (ENABLE_RME == 1) 139 pci: pci@40000000 { 140 #address-cells = <3>; 141 #size-cells = <2>; 142 #interrupt-cells = <1>; 143 compatible = "pci-host-ecam-generic"; 144 device_type = "pci"; 145 reg = <0x0 0x40000000 0x0 0x10000000>; 146 ranges = <0x2000000 0x0 0x50000000 0x0 0x50000000 0x0 0x10000000>, 147 /* First 3GB of 256GB PCIe memory region 2 */ 148 <0x2000000 0x40 0x00000000 0x40 0x00000000 0x0 0xc0000000>; 149 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 150 iommu-map = <0x0 &smmu 0x0 0x10000>; 151 dma-coherent; 152 }; 153 154 smmu: iommu@2b400000 { 155 compatible = "arm,smmu-v3"; 156 reg = <0x0 0x2b400000 0x0 0x100000>; 157 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 158 dma-coherent; 159 #iommu-cells = <1>; 160 }; 161#endif /* ENABLE_RME */ 162}; 163