1NXP S32G274A 2============ 3 4S32G2 is an NXP vehicle network processor combining ASIL D safety, hardware 5security, high-performance real-time and application processing and network 6acceleration. S32G2 supports the needs of new vehicle architectures: 7service-oriented gateways, domain controllers, zonal processors, safety 8processors and more. It is equipped with 4 Cortex-A53 cores operating at 91.0GHz. 10 11The TF-A includes support for one single S32G2-based board called S32G274ARDB2. 12The S32G-VNP-RDB2 is a compact, highly optimized and integrated board 13engineering for vehicle service-oriented gateway (SoG), domain control 14applications, high-performance processing, safety and security applications. 15More details about this board can be found at `s32g274ardb2`_. 16 17Boot Flow 18--------- 19 20:: 21 22 BootROM -> BL2 (SRAM) -> BL31 (DDR) -> BL33 (DDR) 23 24.. warning:: 25 This boot flow is a preliminary version that will serve as a foundation for 26 upcoming S32G2 contributions. 27 28Code Locations 29-------------- 30 31- Downstream TF-A: 32 `link: <https://github.com/nxp-auto-linux/arm-trusted-firmware>`__ 33 34- Downstream U-Boot: 35 `link <https://github.com/nxp-auto-linux/u-boot>`__ 36 37- Downstream Linux: 38 `link <https://github.com/nxp-auto-linux/linux>`__ 39 40How to build 41------------ 42 43The port currently available on the S32G274ARDB2 platform is in its initial 44stage. The boot process takes advantage of both SRAM and DDR memory. BootROM 45loads BL2 into SRAM, and BL2 is responsible for initializing DDR and loading 46subsequent stages (such as BL31 and BL33) into their designated memory regions. 47To create a bootable image, the script below should be used. 48This script makes use of the ``mkimage`` tool, which is part of the U-Boot drop 49for S32G274A SoCs. 50 51.. warning:: 52 The ``DDR_FW_BIN_PATH`` parameter must point to the location of the folder 53 containing the DDR firmware binary specific to the S32G274ARDB2 platform. 54 This binary is essential for proper DDR initialization. It is included in the 55 Linux BSP releases for the S32G274A-RDB board and can be obtained from https://www.nxp.com/. 56 57.. code:: bash 58 59 #!/bin/bash -xe 60 TF_A="${TF_A:-`pwd`}" 61 UBOOT="${UBOOT:-${TF_A}/../u-boot}" 62 DDR_FW="${DDR_FW:-${TF-A}/../ddr-firmware}" 63 DEBUG="${DEBUG:-1}" 64 65 FIP_BASE="0x34100000" 66 67 if [ "${DEBUG}" -eq "1" ]; then 68 BUILD="debug" 69 else 70 BUILD="release" 71 fi 72 73 BOOT_IMAGE="build/s32g274ardb2/${BUILD}/BOOT_IMAGE.bin" 74 BL2_BIN="build/s32g274ardb2/${BUILD}/bl2.bin" 75 FIP_BIN="build/s32g274ardb2/${BUILD}/fip.bin" 76 77 # Generate bl2, bl31 and fip image 78 make -C "${TF_A}" -j9 'PLAT=s32g274ardb2' \ 79 BL33="${UBOOT}/u-boot-nodtb.bin" DEBUG="${DEBUG}" clean DDR_FW_BIN_PATH="${DDR_FW}/ddr_fw_ecc_off.bin" 80 make -C "${TF_A}" -j9 'PLAT=s32g274ardb2' \ 81 BL33="${UBOOT}/u-boot-nodtb.bin" DEBUG="${DEBUG}" bl2 DDR_FW_BIN_PATH="${DDR_FW}/ddr_fw_ecc_off.bin" 82 make -C "${TF_A}" -j9 'PLAT=s32g274ardb2' \ 83 BL33="${UBOOT}/u-boot-nodtb.bin" DEBUG="${DEBUG}" fip DDR_FW_BIN_PATH="${DDR_FW}/ddr_fw_ecc_off.bin" 84 85 # Extract BL2 entry 86 BL2_START="0x$(poetry run memory -p s32g274ardb2 -b debug footprint | \ 87 grep BL2 | awk -F'|' '{print $3}' | xargs)" 88 # BL2 bin file size in bytes 89 BL2_SIZE="$(stat -c "%s" "${BL2_BIN}")" 90 91 # Pack bl2.bin and fip.bin by ensuring that the FIP image will start at FIP_BASE 92 cp -vf "${BL2_BIN}" "${BOOT_IMAGE}" 93 dd if="${FIP_BIN}" of="${BOOT_IMAGE}" seek="$((FIP_BASE - BL2_START))" bs=1 94 95 # Build a bootable image by appending the IVT 96 "${UBOOT}/tools/mkimage" \ 97 -a "${BL2_START}" \ 98 -e "${BL2_START}" \ 99 -T s32ccimage \ 100 -n "${UBOOT}/u-boot-s32.cfgout" \ 101 -d "${BOOT_IMAGE}" \ 102 fip.s32 103 104SoC Errata Workarounds 105---------------------- 106 107The S32G274A port of the TF-A includes compilation flags that can be used to 108control the workaround for the SoC. These flags are used similarly to how the 109:ref:`arm_cpu_macros_errata_workarounds` are used. The list of workarounds 110includes the following switches: 111 112- ``ERRATA_S32_051700``: This applies erratum ERR051700 workaround to 113 SoCs part of the S32 Common Chassis family, and therefore it needs to 114 be enabled for the S32G and S32R devices. 115 116.. _s32g2: https://www.nxp.com/products/processors-and-microcontrollers/s32-automotive-platform/s32g-vehicle-network-processors/s32g2-processors-for-vehicle-networking:S32G2 117.. _s32g274ardb2: https://www.nxp.com/design/design-center/designs/s32g2-vehicle-networking-reference-design:S32G-VNP-RDB2 118