1 /*
2 * Copyright (c) 2022-2026, Arm Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <arch_features.h>
8 #include <common/debug.h>
9 #include <common/feat_detect.h>
10 #include <plat/common/platform.h>
11
12 static bool detection_done[PLATFORM_CORE_COUNT] = { false };
13
14 /*******************************************************************************
15 * Function : check_feature
16 * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and
17 * feature availability on the hardware. <min> is the smallest feature
18 * ID field value that is required for that feature.
19 * Triggers a panic later if a feature is forcefully enabled, but not
20 * available on the PE. Also will panic if the hardware feature ID field
21 * is larger than the maximum known and supported number, specified by <max>.
22 *
23 * We force inlining here to let the compiler optimise away the whole check
24 * if the feature is disabled at build time (FEAT_STATE_DISABLED).
25 ******************************************************************************/
26 static inline bool __attribute((__always_inline__))
check_feature(int state,unsigned long field,const char * feat_name,unsigned int min,unsigned int max)27 check_feature(int state, unsigned long field, const char *feat_name,
28 unsigned int min, unsigned int max)
29 {
30 if (state == FEAT_STATE_ALWAYS && field < min) {
31 ERROR("FEAT_%s not supported by the PE\n", feat_name);
32 return true;
33 }
34 if (state >= FEAT_STATE_ALWAYS && field > max) {
35 ERROR("FEAT_%s is version %ld, but is only known up to version %d\n",
36 feat_name, field, max);
37 return true;
38 }
39
40 return false;
41 }
42
read_feat_rng_trap_id_field(void)43 static unsigned int read_feat_rng_trap_id_field(void)
44 {
45 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT,
46 ID_AA64PFR1_EL1_RNDR_TRAP_MASK);
47 }
48
read_feat_bti_id_field(void)49 static unsigned int read_feat_bti_id_field(void)
50 {
51 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT,
52 ID_AA64PFR1_EL1_BT_MASK);
53 }
54
read_feat_sb_id_field(void)55 static unsigned int read_feat_sb_id_field(void)
56 {
57 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT,
58 ID_AA64ISAR1_SB_MASK);
59 }
60
read_feat_csv2_id_field(void)61 static unsigned int read_feat_csv2_id_field(void)
62 {
63 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT,
64 ID_AA64PFR0_CSV2_MASK);
65 }
66
read_feat_debugv8p9_id_field(void)67 static unsigned int read_feat_debugv8p9_id_field(void)
68 {
69 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_DEBUGVER_SHIFT,
70 ID_AA64DFR0_DEBUGVER_MASK);
71 }
72
read_feat_step2_id_field(void)73 static unsigned int read_feat_step2_id_field(void)
74 {
75 return ISOLATE_FIELD(read_id_aa64dfr2_el1(), ID_AA64DFR2_STEP_SHIFT,
76 ID_AA64DFR2_STEP_MASK);
77 }
78
read_feat_pmuv3_id_field(void)79 static unsigned int read_feat_pmuv3_id_field(void)
80 {
81 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT,
82 ID_AA64DFR0_PMUVER_MASK);
83 }
84
read_feat_vhe_id_field(void)85 static unsigned int read_feat_vhe_id_field(void)
86 {
87 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT,
88 ID_AA64MMFR1_EL1_VHE_MASK);
89 }
90
read_feat_spe_id_field(void)91 static unsigned int read_feat_spe_id_field(void)
92 {
93 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMS_SHIFT,
94 ID_AA64DFR0_PMS_MASK);
95 }
96
read_feat_sve_id_field(void)97 static unsigned int read_feat_sve_id_field(void)
98 {
99 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT,
100 ID_AA64PFR0_SVE_MASK);
101 }
102
read_feat_ras_id_field(void)103 static unsigned int read_feat_ras_id_field(void)
104 {
105 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT,
106 ID_AA64PFR0_RAS_MASK);
107 }
108
read_feat_dit_id_field(void)109 static unsigned int read_feat_dit_id_field(void)
110 {
111 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT,
112 ID_AA64PFR0_DIT_MASK);
113 }
114
read_feat_amu_id_field(void)115 static unsigned int read_feat_amu_id_field(void)
116 {
117 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT,
118 ID_AA64PFR0_AMU_MASK);
119 }
120
read_feat_mpam_version(void)121 static unsigned int read_feat_mpam_version(void)
122 {
123 return (unsigned int)((((read_id_aa64pfr0_el1() >>
124 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) |
125 ((read_id_aa64pfr1_el1() >>
126 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK));
127 }
128
read_feat_nv_id_field(void)129 static unsigned int read_feat_nv_id_field(void)
130 {
131 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT,
132 ID_AA64MMFR2_EL1_NV_MASK);
133 }
134
read_feat_sel2_id_field(void)135 static unsigned int read_feat_sel2_id_field(void)
136 {
137 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT,
138 ID_AA64PFR0_SEL2_MASK);
139 }
140
read_feat_trf_id_field(void)141 static unsigned int read_feat_trf_id_field(void)
142 {
143 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT,
144 ID_AA64DFR0_TRACEFILT_MASK);
145 }
get_armv8_5_mte_support(void)146 static unsigned int get_armv8_5_mte_support(void)
147 {
148 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT,
149 ID_AA64PFR1_EL1_MTE_MASK);
150 }
read_feat_rng_id_field(void)151 static unsigned int read_feat_rng_id_field(void)
152 {
153 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT,
154 ID_AA64ISAR0_RNDR_MASK);
155 }
read_feat_fgt_id_field(void)156 static unsigned int read_feat_fgt_id_field(void)
157 {
158 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT,
159 ID_AA64MMFR0_EL1_FGT_MASK);
160 }
read_feat_ecv_id_field(void)161 static unsigned int read_feat_ecv_id_field(void)
162 {
163 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT,
164 ID_AA64MMFR0_EL1_ECV_MASK);
165 }
read_feat_twed_id_field(void)166 static unsigned int read_feat_twed_id_field(void)
167 {
168 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT,
169 ID_AA64MMFR1_EL1_TWED_MASK);
170 }
171
read_feat_hcx_id_field(void)172 static unsigned int read_feat_hcx_id_field(void)
173 {
174 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT,
175 ID_AA64MMFR1_EL1_HCX_MASK);
176 }
read_feat_ls64_id_field(void)177 static unsigned int read_feat_ls64_id_field(void)
178 {
179 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_LS64_SHIFT,
180 ID_AA64ISAR1_LS64_MASK);
181 }
read_feat_aie_id_field(void)182 static unsigned int read_feat_aie_id_field(void)
183 {
184 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_AIE_SHIFT,
185 ID_AA64MMFR3_EL1_AIE_MASK);
186 }
read_feat_pfar_id_field(void)187 static unsigned int read_feat_pfar_id_field(void)
188 {
189 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_PFAR_SHIFT,
190 ID_AA64PFR1_EL1_PFAR_MASK);
191 }
read_feat_tcr2_id_field(void)192 static unsigned int read_feat_tcr2_id_field(void)
193 {
194 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT,
195 ID_AA64MMFR3_EL1_TCRX_MASK);
196 }
read_feat_s2pie_id_field(void)197 static unsigned int read_feat_s2pie_id_field(void)
198 {
199 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT,
200 ID_AA64MMFR3_EL1_S2PIE_MASK);
201 }
read_feat_s1pie_id_field(void)202 static unsigned int read_feat_s1pie_id_field(void)
203 {
204 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT,
205 ID_AA64MMFR3_EL1_S1PIE_MASK);
206 }
read_feat_s2poe_id_field(void)207 static unsigned int read_feat_s2poe_id_field(void)
208 {
209 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT,
210 ID_AA64MMFR3_EL1_S2POE_MASK);
211 }
read_feat_s1poe_id_field(void)212 static unsigned int read_feat_s1poe_id_field(void)
213 {
214 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT,
215 ID_AA64MMFR3_EL1_S1POE_MASK);
216 }
read_feat_brbe_id_field(void)217 static unsigned int read_feat_brbe_id_field(void)
218 {
219 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT,
220 ID_AA64DFR0_BRBE_MASK);
221 }
read_feat_trbe_id_field(void)222 static unsigned int read_feat_trbe_id_field(void)
223 {
224 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT,
225 ID_AA64DFR0_TRACEBUFFER_MASK);
226 }
read_feat_sme_id_field(void)227 static unsigned int read_feat_sme_id_field(void)
228 {
229 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT,
230 ID_AA64PFR1_EL1_SME_MASK);
231 }
read_feat_gcs_id_field(void)232 static unsigned int read_feat_gcs_id_field(void)
233 {
234 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT,
235 ID_AA64PFR1_EL1_GCS_MASK);
236 }
237
read_feat_rme_id_field(void)238 static unsigned int read_feat_rme_id_field(void)
239 {
240 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT,
241 ID_AA64PFR0_FEAT_RME_MASK);
242 }
243
read_feat_pan_id_field(void)244 static unsigned int read_feat_pan_id_field(void)
245 {
246 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT,
247 ID_AA64MMFR1_EL1_PAN_MASK);
248 }
249
read_feat_mtpmu_id_field(void)250 static unsigned int read_feat_mtpmu_id_field(void)
251 {
252 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT,
253 ID_AA64DFR0_MTPMU_MASK);
254
255 }
256
read_feat_the_id_field(void)257 static unsigned int read_feat_the_id_field(void)
258 {
259 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_THE_SHIFT,
260 ID_AA64PFR1_EL1_THE_MASK);
261 }
262
read_feat_sctlr2_id_field(void)263 static unsigned int read_feat_sctlr2_id_field(void)
264 {
265 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_SCTLR2_SHIFT,
266 ID_AA64MMFR3_EL1_SCTLR2_MASK);
267 }
268
read_feat_d128_id_field(void)269 static unsigned int read_feat_d128_id_field(void)
270 {
271 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT,
272 ID_AA64MMFR3_EL1_D128_MASK);
273 }
read_feat_gcie_id_field(void)274 static unsigned int read_feat_gcie_id_field(void)
275 {
276 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT,
277 ID_AA64PFR2_EL1_GCIE_MASK);
278 }
279
read_feat_ebep_id_field(void)280 static unsigned int read_feat_ebep_id_field(void)
281 {
282 return ISOLATE_FIELD(read_id_aa64dfr1_el1(), ID_AA64DFR1_EBEP_SHIFT,
283 ID_AA64DFR1_EBEP_MASK);
284 }
285
read_feat_fpmr_id_field(void)286 static unsigned int read_feat_fpmr_id_field(void)
287 {
288 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_FPMR_SHIFT,
289 ID_AA64PFR2_EL1_FPMR_MASK);
290 }
291
read_feat_mops_id_field(void)292 static unsigned int read_feat_mops_id_field(void)
293 {
294 return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_EL1_MOPS_SHIFT,
295 ID_AA64ISAR2_EL1_MOPS_MASK);
296 }
297
read_feat_fgwte3_id_field(void)298 static unsigned int read_feat_fgwte3_id_field(void)
299 {
300 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_FGWTE3_SHIFT,
301 ID_AA64MMFR4_EL1_FGWTE3_MASK);
302 }
303
read_feat_cpa_id_field(void)304 static unsigned int read_feat_cpa_id_field(void)
305 {
306 return ISOLATE_FIELD(read_id_aa64isar3_el1(),
307 ID_AA64ISAR3_EL1_CPA_SHIFT,
308 ID_AA64ISAR3_EL1_CPA_MASK);
309 }
310
read_feat_clrbhb_id_field(void)311 static unsigned int read_feat_clrbhb_id_field(void)
312 {
313 return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_CLRBHB_SHIFT,
314 ID_AA64ISAR2_CLRBHB_MASK);
315 }
316
read_feat_rme_gdi_id_field(void)317 static unsigned int read_feat_rme_gdi_id_field(void)
318 {
319 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(),
320 ID_AA64MMFR4_EL1_RME_GDI_SHIFT,
321 ID_AA64MMFR4_EL1_RME_GDI_MASK);
322 }
323
read_feat_idte3_id_field(void)324 static unsigned int read_feat_idte3_id_field(void)
325 {
326 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_IDS_SHIFT,
327 ID_AA64MMFR2_EL1_IDS_MASK);
328 }
329
read_feat_uinj_id_field(void)330 static unsigned int read_feat_uinj_id_field(void)
331 {
332 return ISOLATE_FIELD(read_id_aa64pfr2_el1(),
333 ID_AA64PFR2_EL1_UINJ_SHIFT,
334 ID_AA64PFR2_EL1_UINJ_MASK);
335 }
336
read_feat_lse_id_field(void)337 static unsigned int read_feat_lse_id_field(void)
338 {
339 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_ATOMIC_SHIFT,
340 ID_AA64ISAR0_ATOMIC_MASK);
341 }
342
read_feat_morello_field(void)343 static unsigned int read_feat_morello_field(void)
344 {
345 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_CE_SHIFT,
346 ID_AA64PFR1_EL1_CE_MASK);
347 }
348
read_feat_hdbss_id_field(void)349 static unsigned int read_feat_hdbss_id_field(void)
350 {
351 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HAFDBS_SHIFT,
352 ID_AA64MMFR1_EL1_HAFDBS_MASK);
353 }
354
read_feat_hacdbs_id_field(void)355 static unsigned int read_feat_hacdbs_id_field(void)
356 {
357 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_HACDBS_SHIFT,
358 ID_AA64MMFR4_EL1_HACDBS_MASK);
359 }
360
361 /***********************************************************************************
362 * TF-A supports many Arm architectural features starting from arch version
363 * (8.0 till 8.7+). These features are mostly enabled through build flags. This
364 * mechanism helps in validating these build flags in the early boot phase
365 * either in BL1 or BL31 depending on the platform and assists in identifying
366 * and notifying the features which are enabled but not supported by the PE.
367 *
368 * It reads all the enabled features ID-registers and ensures the features
369 * are supported by the PE.
370 * In case if they aren't it stops booting at an early phase and logs the error
371 * messages, notifying the platforms about the features that are not supported.
372 *
373 * Further the procedure is implemented with a tri-state approach for each feature:
374 * ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time
375 * ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware.
376 * There will be panic if feature is not present at cold boot.
377 * ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime
378 * depending on hardware capability.
379 *
380 * For better readability, state values are defined with macros, namely:
381 * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values
382 * { 0, 1, 2 }, respectively, as their naming.
383 **********************************************************************************/
detect_arch_features(unsigned int core_pos)384 void detect_arch_features(unsigned int core_pos)
385 {
386 /* No need to keep checking after the first time for each core. */
387 if (detection_done[core_pos]) {
388 return;
389 }
390
391 bool tainted = false;
392
393 /* v8.0 features */
394 tainted |= check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(),
395 "SB", 1, 1);
396 tainted |= check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(),
397 "CSV2_2", 2, 3);
398 tainted |= check_feature(ENABLE_FEAT_CLRBHB, read_feat_clrbhb_id_field(),
399 "CLRBHB", 1, 1);
400 /*
401 * Even though the PMUv3 is an OPTIONAL feature, it is always
402 * implemented and Arm prescribes so. So assume it will be there and do
403 * away with a flag for it. This is used to check minor PMUv3px
404 * revisions so that we catch them as they come along
405 */
406 tainted |= check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(),
407 "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9);
408
409 tainted |= check_feature(USE_SPINLOCK_CAS, read_feat_lse_id_field(),
410 "LSE", 2, 3);
411
412 /* v8.1 features */
413 tainted |= check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(),
414 "PAN", 1, 3);
415 tainted |= check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(),
416 "VHE", 1, 1);
417 tainted |= check_feature(ENABLE_SPE_FOR_NS, read_feat_spe_id_field(),
418 "SPE", 1, 6);
419
420 /* v8.2 features */
421 tainted |= check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(),
422 "SVE", 1, 3);
423 tainted |= check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(),
424 "RAS", 1, 3);
425
426 /* v8.3 features */
427 /* the PAuth fields are very complicated, no min/max is checked */
428 tainted |= check_feature(ENABLE_PAUTH, is_feat_pauth_present(),
429 "PAUTH", 1, 1);
430
431 /* v8.4 features */
432 tainted |= check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(),
433 "DIT", 1, 1);
434 tainted |= check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(),
435 "AMUv1", 1, 2);
436 tainted |= check_feature(ENABLE_FEAT_MOPS, read_feat_mops_id_field(),
437 "MOPS", 1, 1);
438 tainted |= check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(),
439 "MPAM", 1, 17);
440 tainted |= check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(),
441 "NV2", 2, 2);
442 tainted |= check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(),
443 "SEL2", 1, 1);
444 tainted |= check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(),
445 "TRF", 1, 1);
446
447 /* v8.5 features */
448 tainted |= check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(),
449 "MTE2", MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY);
450 tainted |= check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(),
451 "RNG", 1, 1);
452 tainted |= check_feature(ENABLE_BTI, read_feat_bti_id_field(),
453 "BTI", 1, 1);
454 tainted |= check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(),
455 "RNG_TRAP", 1, 1);
456
457 /* v8.6 features */
458 tainted |= check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(),
459 "AMUv1p1", 2, 2);
460 tainted |= check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(),
461 "FGT", 1, 2);
462 tainted |= check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(),
463 "FGT2", 2, 2);
464 tainted |= check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(),
465 "ECV", 1, 2);
466 tainted |= check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(),
467 "TWED", 1, 1);
468
469 /*
470 * even though this is a "DISABLE" it does confusingly perform feature
471 * enablement duties like all other flags here. Check it against the HW
472 * feature when we intend to diverge from the default behaviour
473 */
474 tainted |= check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(),
475 "MTPMU", 1, 15);
476 if (read_feat_mtpmu_id_field() == 15) {
477 WARN("DISABLE_MTPMU is implemented in hardware, flag is redundant.\n");
478 }
479
480 /* v8.7 features */
481 tainted |= check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(),
482 "HCX", 1, 1);
483 tainted |= check_feature(ENABLE_FEAT_LS64_ACCDATA, read_feat_ls64_id_field(),
484 "LS64", 1, 3);
485
486 /* v8.9 features */
487 tainted |= check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(),
488 "TCR2", 1, 1);
489 tainted |= check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(),
490 "S2PIE", 1, 1);
491 tainted |= check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(),
492 "S1PIE", 1, 1);
493 tainted |= check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(),
494 "S2POE", 1, 1);
495 tainted |= check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(),
496 "S1POE", 1, 1);
497 tainted |= check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(),
498 "CSV2_3", 3, 3);
499 tainted |= check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(),
500 "DEBUGV8P9", 11, 11);
501 tainted |= check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(),
502 "THE", 1, 1);
503 tainted |= check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(),
504 "SCTLR2", 1, 1);
505 tainted |= check_feature(ENABLE_FEAT_AIE, read_feat_aie_id_field(),
506 "AIE", 1, 1);
507 tainted |= check_feature(ENABLE_FEAT_PFAR, read_feat_pfar_id_field(),
508 "PFAR", 1, 1);
509
510 /* v9.0 features */
511 tainted |= check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(),
512 "BRBE", 1, 2);
513 tainted |= check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(),
514 "TRBE", 1, 2);
515 tainted |= check_feature(ENABLE_FEAT_UINJ, read_feat_uinj_id_field(),
516 "UINJ", 1, 1);
517
518 /* v9.2 features */
519 tainted |= check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(),
520 "SME", 1, 2);
521 tainted |= check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(),
522 "SME2", 2, 3);
523 tainted |= check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(),
524 "FPMR", 1, 1);
525 tainted |= check_feature(ENABLE_FEAT_RME, read_feat_rme_id_field(),
526 "RME", 1, 2);
527
528 /* v9.3 features */
529 tainted |= check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(),
530 "D128", 1, 1);
531 tainted |= check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(),
532 "GCIE", 1, 1);
533 tainted |= check_feature(ENABLE_FEAT_MPAM_PE_BW_CTRL,
534 is_feat_mpam_pe_bw_ctrl_present(),
535 "MPAM_PE_BW_CTRL", 1, 1);
536 tainted |= check_feature(ENABLE_FEAT_EBEP, read_feat_ebep_id_field(),
537 "EBEP", 1, 1);
538
539 /* v9.4 features */
540 tainted |= check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(),
541 "GCS", 1, 1);
542 tainted |= check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(),
543 "PAUTH_LR", 1, 1);
544 tainted |= check_feature(ENABLE_FEAT_FGWTE3, read_feat_fgwte3_id_field(),
545 "FGWTE3", 1, 1);
546 tainted |= check_feature(ENABLE_FEAT_CPA2, read_feat_cpa_id_field(),
547 "CPA2", 2, 2);
548 tainted |= check_feature(ENABLE_FEAT_RME_GDI, read_feat_rme_gdi_id_field(),
549 "RME_GDI", 1, 1);
550 tainted |= check_feature(ENABLE_FEAT_IDTE3, read_feat_idte3_id_field(),
551 "IDTE3", 2, 2);
552 tainted |= check_feature(ENABLE_FEAT_STEP2, read_feat_step2_id_field(),
553 "STEP2", 1, 1);
554 tainted |= check_feature(ENABLE_FEAT_HDBSS, read_feat_hdbss_id_field(),
555 "HDBSS", 4, 4);
556 tainted |= check_feature(ENABLE_FEAT_HACDBS, read_feat_hacdbs_id_field(),
557 "HACDBS", 1, 1);
558
559 /* Morello Arch feature */
560 tainted |= check_feature(ENABLE_FEAT_MORELLO, read_feat_morello_field(),
561 "MORELLO_ARCH", 1, 1);
562
563 if (tainted) {
564 panic();
565 }
566
567 detection_done[core_pos] = true;
568 }
569