1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (C) 2024, STMicroelectronics
4 */
5
6 #include <assert.h>
7 #include <config.h>
8 #include <drivers/clk_dt.h>
9 #include <drivers/stm32_rif.h>
10 #include <drivers/stm32_shared_io.h>
11 #include <drivers/stm32mp25_rcc.h>
12 #include <drivers/stm32mp_dt_bindings.h>
13 #include <initcall.h>
14 #include <io.h>
15 #include <kernel/dt.h>
16 #include <kernel/panic.h>
17 #include <kernel/pm.h>
18 #include <libfdt.h>
19 #include <stdbool.h>
20 #include <stdio.h>
21 #include <stm32_sysconf.h>
22 #include <stm32_util.h>
23 #include <trace.h>
24 #include <util.h>
25
26 #include "clk-stm32-core.h"
27
28 #define MAX_OPP CFG_STM32MP_OPP_COUNT
29
30 #define RCC_SECCFGR(x) (U(0x0) + U(0x4) * (x))
31 #define RCC_PRIVCFGR(x) (U(0x10) + U(0x4) * (x))
32 #define RCC_RCFGLOCKR(x) (U(0x20) + U(0x4) * (x))
33 #define RCC_CIDCFGR(x) (U(0x030) + U(0x08) * (x))
34 #define RCC_SEMCR(x) (U(0x034) + U(0x08) * (x))
35
36 #define TIMEOUT_US_100MS U(100000)
37 #define TIMEOUT_US_200MS U(200000)
38 #define TIMEOUT_US_1S U(1000000)
39
40 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS
41 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS
42 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS
43 #define OSCRDY_TIMEOUT TIMEOUT_US_1S
44
45 /* PLL minimal frequencies for clock sources */
46 #define PLL_REFCLK_MIN UL(5000000)
47 #define PLL_FRAC_REFCLK_MIN UL(10000000)
48
49 /* Parameters from XBAR_CFG in st,cksrc field */
50 #define XBAR_CKSRC_CHANNEL GENMASK_32(5, 0)
51 #define XBAR_CKSRC_SRC GENMASK_32(9, 6)
52 #define XBAR_CKSRC_SRC_OFFSET U(6)
53 #define XBAR_CKSRC_PREDIV GENMASK_32(19, 10)
54 #define XBAR_CKSRC_PREDIV_OFFSET U(10)
55 #define XBAR_CKSRC_FINDIV GENMASK_32(25, 20)
56 #define XBAR_CKSRC_FINDIV_OFFSET U(20)
57
58 #define XBAR_CHANNEL_NB U(64)
59 #define XBAR_ROOT_CHANNEL_NB U(7)
60
61 #define FLEX_STGEN U(33)
62
63 #define RCC_0_MHZ UL(0)
64 #define RCC_4_MHZ UL(4000000)
65 #define RCC_16_MHZ UL(16000000)
66
67 /* CIDCFGR register bitfields */
68 #define RCC_CIDCFGR_SEMWL_MASK GENMASK_32(23, 16)
69 #define RCC_CIDCFGR_SCID_MASK GENMASK_32(6, 4)
70 #define RCC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \
71 _CIDCFGR_SEMEN | \
72 RCC_CIDCFGR_SCID_MASK |\
73 RCC_CIDCFGR_SEMWL_MASK)
74
75 /* SECCFGR register bitfields */
76 #define RCC_SECCFGR_EN BIT(0)
77
78 /* SEMCR register bitfields */
79 #define RCC_SEMCR_SCID_MASK GENMASK_32(6, 4)
80 #define RCC_SEMCR_SCID_SHIFT U(4)
81
82 /* RIF miscellaneous */
83 #define RCC_NB_RIF_RES U(114)
84 #define RCC_NB_CONFS ROUNDUP_DIV(RCC_NB_RIF_RES, 32)
85
86 enum pll_cfg {
87 FBDIV,
88 REFDIV,
89 POSTDIV1,
90 POSTDIV2,
91 PLLCFG_NB
92 };
93
94 enum pll_csg {
95 DIVVAL,
96 SPREAD,
97 DOWNSPREAD,
98 PLLCSG_NB
99 };
100
101 struct stm32_pll_dt_cfg {
102 bool enabled;
103 uint32_t cfg[PLLCFG_NB];
104 uint32_t csg[PLLCSG_NB];
105 uint32_t frac;
106 bool csg_enabled;
107 uint32_t src;
108 };
109
110 struct stm32_osci_dt_cfg {
111 unsigned long freq;
112 bool bypass;
113 bool digbyp;
114 bool css;
115 uint32_t drive;
116 };
117
118 struct stm32_clk_opp_cfg {
119 uint32_t frq;
120 uint32_t src;
121 struct stm32_pll_dt_cfg pll_cfg;
122 };
123
124 struct stm32_clk_opp_dt_cfg {
125 struct stm32_clk_opp_cfg cpu1_opp[MAX_OPP];
126 };
127
128 struct stm32_clk_platdata {
129 uintptr_t rcc_base;
130 uint32_t nosci;
131 struct stm32_osci_dt_cfg *osci;
132 uint32_t npll;
133 struct stm32_pll_dt_cfg *pll;
134 struct stm32_clk_opp_dt_cfg *opp;
135 struct rif_conf_data conf_data;
136 unsigned int nb_res;
137 uint32_t nbusclk;
138 uint32_t *busclk;
139 uint32_t nkernelclk;
140 uint32_t *kernelclk;
141 uint32_t nflexgen;
142 uint32_t *flexgen;
143 uint32_t c1msrd;
144 bool safe_rst;
145 };
146
147 /*
148 * GATE CONFIG
149 */
150
151 /* WARNING GATE_XXX_RDY MUST FOLLOW GATE_XXX */
152
153 enum enum_gate_cfg {
154 GATE_HSI,
155 GATE_HSI_RDY,
156 GATE_HSE,
157 GATE_HSE_RDY,
158 GATE_LSE,
159 GATE_LSE_RDY,
160 GATE_LSI,
161 GATE_LSI_RDY,
162 GATE_MSI,
163 GATE_MSI_RDY,
164 GATE_PLL1,
165 GATE_PLL1_RDY,
166 GATE_PLL2,
167 GATE_PLL2_RDY,
168 GATE_PLL3,
169 GATE_PLL3_RDY,
170 GATE_PLL4,
171 GATE_PLL4_RDY,
172 GATE_PLL5,
173 GATE_PLL5_RDY,
174 GATE_PLL6,
175 GATE_PLL6_RDY,
176 GATE_PLL7,
177 GATE_PLL7_RDY,
178 GATE_PLL8,
179 GATE_PLL8_RDY,
180 GATE_PLL4_CKREFST,
181 GATE_PLL5_CKREFST,
182 GATE_PLL6_CKREFST,
183 GATE_PLL7_CKREFST,
184 GATE_PLL8_CKREFST,
185 GATE_HSEDIV2,
186 GATE_APB1DIV_RDY,
187 GATE_APB2DIV_RDY,
188 GATE_APB3DIV_RDY,
189 GATE_APB4DIV_RDY,
190 GATE_APBDBGDIV_RDY,
191 GATE_TIMG1PRE_RDY,
192 GATE_TIMG2PRE_RDY,
193 GATE_LSMCUDIV_RDY,
194 GATE_RTCCK,
195 GATE_C3,
196 GATE_LPTIM3C3,
197 GATE_LPTIM4C3,
198 GATE_LPTIM5C3,
199 GATE_SPI8C3,
200 GATE_LPUART1C3,
201 GATE_I2C8C3,
202 GATE_ADF1C3,
203 GATE_GPIOZC3,
204 GATE_LPDMAC3,
205 GATE_RTCC3,
206 GATE_I3C4C3,
207 GATE_MCO1,
208 GATE_MCO2,
209 GATE_DDRCP,
210 GATE_DDRCAPB,
211 GATE_DDRPHYCAPB,
212 GATE_DDRPHYC,
213 GATE_DDRCFG,
214 GATE_SYSRAM,
215 GATE_VDERAM,
216 GATE_SRAM1,
217 GATE_SRAM2,
218 GATE_RETRAM,
219 GATE_BKPSRAM,
220 GATE_LPSRAM1,
221 GATE_LPSRAM2,
222 GATE_LPSRAM3,
223 GATE_OSPI1,
224 GATE_OSPI2,
225 GATE_FMC,
226 GATE_DBG,
227 GATE_TRACE,
228 GATE_STM,
229 GATE_ETR,
230 GATE_GPIOA,
231 GATE_GPIOB,
232 GATE_GPIOC,
233 GATE_GPIOD,
234 GATE_GPIOE,
235 GATE_GPIOF,
236 GATE_GPIOG,
237 GATE_GPIOH,
238 GATE_GPIOI,
239 GATE_GPIOJ,
240 GATE_GPIOK,
241 GATE_GPIOZ,
242 GATE_HPDMA1,
243 GATE_HPDMA2,
244 GATE_HPDMA3,
245 GATE_LPDMA,
246 GATE_HSEM,
247 GATE_IPCC1,
248 GATE_IPCC2,
249 GATE_RTC,
250 GATE_SYSCPU1,
251 GATE_BSEC,
252 GATE_IS2M,
253 GATE_HSIMON,
254 GATE_TIM1,
255 GATE_TIM2,
256 GATE_TIM3,
257 GATE_TIM4,
258 GATE_TIM5,
259 GATE_TIM6,
260 GATE_TIM7,
261 GATE_TIM8,
262 GATE_TIM10,
263 GATE_TIM11,
264 GATE_TIM12,
265 GATE_TIM13,
266 GATE_TIM14,
267 GATE_TIM15,
268 GATE_TIM16,
269 GATE_TIM17,
270 GATE_TIM20,
271 GATE_LPTIM1,
272 GATE_LPTIM2,
273 GATE_LPTIM3,
274 GATE_LPTIM4,
275 GATE_LPTIM5,
276 GATE_SPI1,
277 GATE_SPI2,
278 GATE_SPI3,
279 GATE_SPI4,
280 GATE_SPI5,
281 GATE_SPI6,
282 GATE_SPI7,
283 GATE_SPI8,
284 GATE_SPDIFRX,
285 GATE_USART1,
286 GATE_USART2,
287 GATE_USART3,
288 GATE_UART4,
289 GATE_UART5,
290 GATE_USART6,
291 GATE_UART7,
292 GATE_UART8,
293 GATE_UART9,
294 GATE_LPUART1,
295 GATE_I2C1,
296 GATE_I2C2,
297 GATE_I2C3,
298 GATE_I2C4,
299 GATE_I2C5,
300 GATE_I2C6,
301 GATE_I2C7,
302 GATE_I2C8,
303 GATE_SAI1,
304 GATE_SAI2,
305 GATE_SAI3,
306 GATE_SAI4,
307 GATE_MDF1,
308 GATE_ADF1,
309 GATE_FDCAN,
310 GATE_HDP,
311 GATE_ADC12,
312 GATE_ADC3,
313 GATE_ETH1MAC,
314 GATE_ETH1,
315 GATE_ETH1TX,
316 GATE_ETH1RX,
317 GATE_ETH1STP,
318 GATE_ETH2MAC,
319 GATE_ETH2,
320 GATE_ETH2STP,
321 GATE_ETH2TX,
322 GATE_ETH2RX,
323 GATE_USB2,
324 GATE_USB2PHY1,
325 GATE_USB2PHY2,
326 GATE_USB3DR,
327 GATE_USB3PCIEPHY,
328 GATE_PCIE,
329 GATE_USBTC,
330 GATE_ETHSWMAC,
331 GATE_ETHSW,
332 GATE_ETHSWREF,
333 GATE_STGEN,
334 GATE_SDMMC1,
335 GATE_SDMMC2,
336 GATE_SDMMC3,
337 GATE_GPU,
338 GATE_LTDC,
339 GATE_DSI,
340 GATE_LVDS,
341 GATE_CSI,
342 GATE_DCMIPP,
343 GATE_CCI,
344 GATE_VDEC,
345 GATE_VENC,
346 GATE_RNG,
347 GATE_PKA,
348 GATE_SAES,
349 GATE_HASH,
350 GATE_CRYP1,
351 GATE_CRYP2,
352 GATE_IWDG1,
353 GATE_IWDG2,
354 GATE_IWDG3,
355 GATE_IWDG4,
356 GATE_IWDG5,
357 GATE_WWDG1,
358 GATE_WWDG2,
359 GATE_VREF,
360 GATE_DTS,
361 GATE_CRC,
362 GATE_SERC,
363 GATE_OSPIIOM,
364 GATE_GICV2M,
365 GATE_I3C1,
366 GATE_I3C2,
367 GATE_I3C3,
368 GATE_I3C4,
369 GATE_NB
370 };
371
372 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\
373 [(_id)] = {\
374 .offset = (_offset),\
375 .bit_idx = (_bit_idx),\
376 .set_clr = (_offset_clr),\
377 }
378
379 static const struct gate_cfg gates_mp25[GATE_NB] = {
380 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0),
381 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0),
382 GATE_CFG(GATE_LSI, RCC_BDCR, 9, 0),
383 GATE_CFG(GATE_LSI_RDY, RCC_BDCR, 10, 0),
384 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0),
385 GATE_CFG(GATE_MSI, RCC_D3DCR, 0, 0),
386 GATE_CFG(GATE_MSI_RDY, RCC_D3DCR, 2, 0),
387 GATE_CFG(GATE_PLL1, RCC_PLL2CFGR1, 8, 0),
388 GATE_CFG(GATE_PLL1_RDY, RCC_PLL2CFGR1, 24, 0),
389 GATE_CFG(GATE_PLL2, RCC_PLL2CFGR1, 8, 0),
390 GATE_CFG(GATE_PLL2_RDY, RCC_PLL2CFGR1, 24, 0),
391 GATE_CFG(GATE_PLL3, RCC_PLL3CFGR1, 8, 0),
392 GATE_CFG(GATE_PLL3_RDY, RCC_PLL3CFGR1, 24, 0),
393 GATE_CFG(GATE_PLL4, RCC_PLL4CFGR1, 8, 0),
394 GATE_CFG(GATE_PLL4_RDY, RCC_PLL4CFGR1, 24, 0),
395 GATE_CFG(GATE_PLL5, RCC_PLL5CFGR1, 8, 0),
396 GATE_CFG(GATE_PLL5_RDY, RCC_PLL5CFGR1, 24, 0),
397 GATE_CFG(GATE_PLL6, RCC_PLL6CFGR1, 8, 0),
398 GATE_CFG(GATE_PLL6_RDY, RCC_PLL6CFGR1, 24, 0),
399 GATE_CFG(GATE_PLL7, RCC_PLL7CFGR1, 8, 0),
400 GATE_CFG(GATE_PLL7_RDY, RCC_PLL7CFGR1, 24, 0),
401 GATE_CFG(GATE_PLL8, RCC_PLL8CFGR1, 8, 0),
402 GATE_CFG(GATE_PLL8_RDY, RCC_PLL8CFGR1, 24, 0),
403 GATE_CFG(GATE_PLL4_CKREFST, RCC_PLL4CFGR1, 28, 0),
404 GATE_CFG(GATE_PLL5_CKREFST, RCC_PLL5CFGR1, 28, 0),
405 GATE_CFG(GATE_PLL6_CKREFST, RCC_PLL6CFGR1, 28, 0),
406 GATE_CFG(GATE_PLL7_CKREFST, RCC_PLL7CFGR1, 28, 0),
407 GATE_CFG(GATE_PLL8_CKREFST, RCC_PLL8CFGR1, 28, 0),
408 GATE_CFG(GATE_C3, RCC_C3CFGR, 1, 0),
409 GATE_CFG(GATE_LPTIM3C3, RCC_C3CFGR, 16, 0),
410 GATE_CFG(GATE_LPTIM4C3, RCC_C3CFGR, 17, 0),
411 GATE_CFG(GATE_LPTIM5C3, RCC_C3CFGR, 18, 0),
412 GATE_CFG(GATE_SPI8C3, RCC_C3CFGR, 19, 0),
413 GATE_CFG(GATE_LPUART1C3, RCC_C3CFGR, 20, 0),
414 GATE_CFG(GATE_I2C8C3, RCC_C3CFGR, 21, 0),
415 GATE_CFG(GATE_ADF1C3, RCC_C3CFGR, 23, 0),
416 GATE_CFG(GATE_GPIOZC3, RCC_C3CFGR, 24, 0),
417 GATE_CFG(GATE_LPDMAC3, RCC_C3CFGR, 25, 0),
418 GATE_CFG(GATE_RTCC3, RCC_C3CFGR, 26, 0),
419 GATE_CFG(GATE_I3C4C3, RCC_C3CFGR, 27, 0),
420 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 8, 0),
421 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 8, 0),
422 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1),
423 GATE_CFG(GATE_HSEDIV2, RCC_OCENSETR, 5, 1),
424 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1),
425 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0),
426 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0),
427 GATE_CFG(GATE_APB1DIV_RDY, RCC_APB1DIVR, 31, 0),
428 GATE_CFG(GATE_APB2DIV_RDY, RCC_APB2DIVR, 31, 0),
429 GATE_CFG(GATE_APB3DIV_RDY, RCC_APB3DIVR, 31, 0),
430 GATE_CFG(GATE_APB4DIV_RDY, RCC_APB4DIVR, 31, 0),
431 GATE_CFG(GATE_APBDBGDIV_RDY, RCC_APBDBGDIVR, 31, 0),
432 GATE_CFG(GATE_TIMG1PRE_RDY, RCC_TIMG1PRER, 31, 0),
433 GATE_CFG(GATE_TIMG2PRE_RDY, RCC_TIMG2PRER, 31, 0),
434 GATE_CFG(GATE_LSMCUDIV_RDY, RCC_LSMCUDIVR, 31, 0),
435 GATE_CFG(GATE_DDRCP, RCC_DDRCPCFGR, 1, 0),
436 GATE_CFG(GATE_DDRCAPB, RCC_DDRCAPBCFGR, 1, 0),
437 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRPHYCAPBCFGR, 1, 0),
438 GATE_CFG(GATE_DDRPHYC, RCC_DDRPHYCCFGR, 1, 0),
439 GATE_CFG(GATE_DDRCFG, RCC_DDRCFGR, 1, 0),
440 GATE_CFG(GATE_SYSRAM, RCC_SYSRAMCFGR, 1, 0),
441 GATE_CFG(GATE_VDERAM, RCC_VDERAMCFGR, 1, 0),
442 GATE_CFG(GATE_SRAM1, RCC_SRAM1CFGR, 1, 0),
443 GATE_CFG(GATE_SRAM2, RCC_SRAM2CFGR, 1, 0),
444 GATE_CFG(GATE_RETRAM, RCC_RETRAMCFGR, 1, 0),
445 GATE_CFG(GATE_BKPSRAM, RCC_BKPSRAMCFGR, 1, 0),
446 GATE_CFG(GATE_LPSRAM1, RCC_LPSRAM1CFGR, 1, 0),
447 GATE_CFG(GATE_LPSRAM2, RCC_LPSRAM2CFGR, 1, 0),
448 GATE_CFG(GATE_LPSRAM3, RCC_LPSRAM3CFGR, 1, 0),
449 GATE_CFG(GATE_OSPI1, RCC_OSPI1CFGR, 1, 0),
450 GATE_CFG(GATE_OSPI2, RCC_OSPI2CFGR, 1, 0),
451 GATE_CFG(GATE_FMC, RCC_FMCCFGR, 1, 0),
452 GATE_CFG(GATE_DBG, RCC_DBGCFGR, 8, 0),
453 GATE_CFG(GATE_TRACE, RCC_DBGCFGR, 9, 0),
454 GATE_CFG(GATE_STM, RCC_STMCFGR, 1, 0),
455 GATE_CFG(GATE_ETR, RCC_ETRCFGR, 1, 0),
456 GATE_CFG(GATE_GPIOA, RCC_GPIOACFGR, 1, 0),
457 GATE_CFG(GATE_GPIOB, RCC_GPIOBCFGR, 1, 0),
458 GATE_CFG(GATE_GPIOC, RCC_GPIOCCFGR, 1, 0),
459 GATE_CFG(GATE_GPIOD, RCC_GPIODCFGR, 1, 0),
460 GATE_CFG(GATE_GPIOE, RCC_GPIOECFGR, 1, 0),
461 GATE_CFG(GATE_GPIOF, RCC_GPIOFCFGR, 1, 0),
462 GATE_CFG(GATE_GPIOG, RCC_GPIOGCFGR, 1, 0),
463 GATE_CFG(GATE_GPIOH, RCC_GPIOHCFGR, 1, 0),
464 GATE_CFG(GATE_GPIOI, RCC_GPIOICFGR, 1, 0),
465 GATE_CFG(GATE_GPIOJ, RCC_GPIOJCFGR, 1, 0),
466 GATE_CFG(GATE_GPIOK, RCC_GPIOKCFGR, 1, 0),
467 GATE_CFG(GATE_GPIOZ, RCC_GPIOZCFGR, 1, 0),
468 GATE_CFG(GATE_HPDMA1, RCC_HPDMA1CFGR, 1, 0),
469 GATE_CFG(GATE_HPDMA2, RCC_HPDMA2CFGR, 1, 0),
470 GATE_CFG(GATE_HPDMA3, RCC_HPDMA3CFGR, 1, 0),
471 GATE_CFG(GATE_LPDMA, RCC_LPDMACFGR, 1, 0),
472 GATE_CFG(GATE_HSEM, RCC_HSEMCFGR, 1, 0),
473 GATE_CFG(GATE_IPCC1, RCC_IPCC1CFGR, 1, 0),
474 GATE_CFG(GATE_IPCC2, RCC_IPCC2CFGR, 1, 0),
475 GATE_CFG(GATE_RTC, RCC_RTCCFGR, 1, 0),
476 GATE_CFG(GATE_SYSCPU1, RCC_SYSCPU1CFGR, 1, 0),
477 GATE_CFG(GATE_BSEC, RCC_BSECCFGR, 1, 0),
478 GATE_CFG(GATE_IS2M, RCC_IS2MCFGR, 1, 0),
479 GATE_CFG(GATE_HSIMON, RCC_HSIFMONCR, 15, 0),
480 GATE_CFG(GATE_TIM1, RCC_TIM1CFGR, 1, 0),
481 GATE_CFG(GATE_TIM2, RCC_TIM2CFGR, 1, 0),
482 GATE_CFG(GATE_TIM3, RCC_TIM3CFGR, 1, 0),
483 GATE_CFG(GATE_TIM4, RCC_TIM4CFGR, 1, 0),
484 GATE_CFG(GATE_TIM5, RCC_TIM5CFGR, 1, 0),
485 GATE_CFG(GATE_TIM6, RCC_TIM6CFGR, 1, 0),
486 GATE_CFG(GATE_TIM7, RCC_TIM7CFGR, 1, 0),
487 GATE_CFG(GATE_TIM8, RCC_TIM8CFGR, 1, 0),
488 GATE_CFG(GATE_TIM10, RCC_TIM10CFGR, 1, 0),
489 GATE_CFG(GATE_TIM11, RCC_TIM11CFGR, 1, 0),
490 GATE_CFG(GATE_TIM12, RCC_TIM12CFGR, 1, 0),
491 GATE_CFG(GATE_TIM13, RCC_TIM13CFGR, 1, 0),
492 GATE_CFG(GATE_TIM14, RCC_TIM14CFGR, 1, 0),
493 GATE_CFG(GATE_TIM15, RCC_TIM15CFGR, 1, 0),
494 GATE_CFG(GATE_TIM16, RCC_TIM16CFGR, 1, 0),
495 GATE_CFG(GATE_TIM17, RCC_TIM17CFGR, 1, 0),
496 GATE_CFG(GATE_TIM20, RCC_TIM20CFGR, 1, 0),
497 GATE_CFG(GATE_LPTIM1, RCC_LPTIM1CFGR, 1, 0),
498 GATE_CFG(GATE_LPTIM2, RCC_LPTIM2CFGR, 1, 0),
499 GATE_CFG(GATE_LPTIM3, RCC_LPTIM3CFGR, 1, 0),
500 GATE_CFG(GATE_LPTIM4, RCC_LPTIM4CFGR, 1, 0),
501 GATE_CFG(GATE_LPTIM5, RCC_LPTIM5CFGR, 1, 0),
502 GATE_CFG(GATE_SPI1, RCC_SPI1CFGR, 1, 0),
503 GATE_CFG(GATE_SPI2, RCC_SPI2CFGR, 1, 0),
504 GATE_CFG(GATE_SPI3, RCC_SPI3CFGR, 1, 0),
505 GATE_CFG(GATE_SPI4, RCC_SPI4CFGR, 1, 0),
506 GATE_CFG(GATE_SPI5, RCC_SPI5CFGR, 1, 0),
507 GATE_CFG(GATE_SPI6, RCC_SPI6CFGR, 1, 0),
508 GATE_CFG(GATE_SPI7, RCC_SPI7CFGR, 1, 0),
509 GATE_CFG(GATE_SPI8, RCC_SPI8CFGR, 1, 0),
510 GATE_CFG(GATE_SPDIFRX, RCC_SPDIFRXCFGR, 1, 0),
511 GATE_CFG(GATE_USART1, RCC_USART1CFGR, 1, 0),
512 GATE_CFG(GATE_USART2, RCC_USART2CFGR, 1, 0),
513 GATE_CFG(GATE_USART3, RCC_USART3CFGR, 1, 0),
514 GATE_CFG(GATE_UART4, RCC_UART4CFGR, 1, 0),
515 GATE_CFG(GATE_UART5, RCC_UART5CFGR, 1, 0),
516 GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0),
517 GATE_CFG(GATE_UART7, RCC_UART7CFGR, 1, 0),
518 GATE_CFG(GATE_UART8, RCC_UART8CFGR, 1, 0),
519 GATE_CFG(GATE_UART9, RCC_UART9CFGR, 1, 0),
520 GATE_CFG(GATE_LPUART1, RCC_LPUART1CFGR, 1, 0),
521 GATE_CFG(GATE_I2C1, RCC_I2C1CFGR, 1, 0),
522 GATE_CFG(GATE_I2C2, RCC_I2C2CFGR, 1, 0),
523 GATE_CFG(GATE_I2C3, RCC_I2C3CFGR, 1, 0),
524 GATE_CFG(GATE_I2C4, RCC_I2C4CFGR, 1, 0),
525 GATE_CFG(GATE_I2C5, RCC_I2C5CFGR, 1, 0),
526 GATE_CFG(GATE_I2C6, RCC_I2C6CFGR, 1, 0),
527 GATE_CFG(GATE_I2C7, RCC_I2C7CFGR, 1, 0),
528 GATE_CFG(GATE_I2C8, RCC_I2C8CFGR, 1, 0),
529 GATE_CFG(GATE_SAI1, RCC_SAI1CFGR, 1, 0),
530 GATE_CFG(GATE_SAI2, RCC_SAI2CFGR, 1, 0),
531 GATE_CFG(GATE_SAI3, RCC_SAI3CFGR, 1, 0),
532 GATE_CFG(GATE_SAI4, RCC_SAI4CFGR, 1, 0),
533 GATE_CFG(GATE_MDF1, RCC_MDF1CFGR, 1, 0),
534 GATE_CFG(GATE_ADF1, RCC_ADF1CFGR, 1, 0),
535 GATE_CFG(GATE_FDCAN, RCC_FDCANCFGR, 1, 0),
536 GATE_CFG(GATE_HDP, RCC_HDPCFGR, 1, 0),
537 GATE_CFG(GATE_ADC12, RCC_ADC12CFGR, 1, 0),
538 GATE_CFG(GATE_ADC3, RCC_ADC3CFGR, 1, 0),
539 GATE_CFG(GATE_ETH1MAC, RCC_ETH1CFGR, 1, 0),
540 GATE_CFG(GATE_ETH1STP, RCC_ETH1CFGR, 4, 0),
541 GATE_CFG(GATE_ETH1, RCC_ETH1CFGR, 5, 0),
542 GATE_CFG(GATE_ETH1TX, RCC_ETH1CFGR, 8, 0),
543 GATE_CFG(GATE_ETH1RX, RCC_ETH1CFGR, 10, 0),
544 GATE_CFG(GATE_ETH2MAC, RCC_ETH2CFGR, 1, 0),
545 GATE_CFG(GATE_ETH2STP, RCC_ETH2CFGR, 4, 0),
546 GATE_CFG(GATE_ETH2, RCC_ETH2CFGR, 5, 0),
547 GATE_CFG(GATE_ETH2TX, RCC_ETH2CFGR, 8, 0),
548 GATE_CFG(GATE_ETH2RX, RCC_ETH2CFGR, 10, 0),
549 GATE_CFG(GATE_USB2, RCC_USB2CFGR, 1, 0),
550 GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0),
551 GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0),
552 GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0),
553 GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0),
554 GATE_CFG(GATE_PCIE, RCC_PCIECFGR, 1, 0),
555 GATE_CFG(GATE_USBTC, RCC_USBTCCFGR, 1, 0),
556 GATE_CFG(GATE_ETHSWMAC, RCC_ETHSWCFGR, 1, 0),
557 GATE_CFG(GATE_ETHSW, RCC_ETHSWCFGR, 5, 0),
558 GATE_CFG(GATE_ETHSWREF, RCC_ETHSWCFGR, 21, 0),
559 GATE_CFG(GATE_STGEN, RCC_STGENCFGR, 1, 0),
560 GATE_CFG(GATE_SDMMC1, RCC_SDMMC1CFGR, 1, 0),
561 GATE_CFG(GATE_SDMMC2, RCC_SDMMC2CFGR, 1, 0),
562 GATE_CFG(GATE_SDMMC3, RCC_SDMMC3CFGR, 1, 0),
563 GATE_CFG(GATE_GPU, RCC_GPUCFGR, 1, 0),
564 GATE_CFG(GATE_LTDC, RCC_LTDCCFGR, 1, 0),
565 GATE_CFG(GATE_DSI, RCC_DSICFGR, 1, 0),
566 GATE_CFG(GATE_LVDS, RCC_LVDSCFGR, 1, 0),
567 GATE_CFG(GATE_CSI, RCC_CSICFGR, 1, 0),
568 GATE_CFG(GATE_DCMIPP, RCC_DCMIPPCFGR, 1, 0),
569 GATE_CFG(GATE_CCI, RCC_CCICFGR, 1, 0),
570 GATE_CFG(GATE_VDEC, RCC_VDECCFGR, 1, 0),
571 GATE_CFG(GATE_VENC, RCC_VENCCFGR, 1, 0),
572 GATE_CFG(GATE_RNG, RCC_RNGCFGR, 1, 0),
573 GATE_CFG(GATE_PKA, RCC_PKACFGR, 1, 0),
574 GATE_CFG(GATE_SAES, RCC_SAESCFGR, 1, 0),
575 GATE_CFG(GATE_HASH, RCC_HASHCFGR, 1, 0),
576 GATE_CFG(GATE_CRYP1, RCC_CRYP1CFGR, 1, 0),
577 GATE_CFG(GATE_CRYP2, RCC_CRYP2CFGR, 1, 0),
578 GATE_CFG(GATE_IWDG1, RCC_IWDG1CFGR, 1, 0),
579 GATE_CFG(GATE_IWDG2, RCC_IWDG2CFGR, 1, 0),
580 GATE_CFG(GATE_IWDG3, RCC_IWDG3CFGR, 1, 0),
581 GATE_CFG(GATE_IWDG4, RCC_IWDG4CFGR, 1, 0),
582 GATE_CFG(GATE_IWDG5, RCC_IWDG5CFGR, 1, 0),
583 GATE_CFG(GATE_WWDG1, RCC_WWDG1CFGR, 1, 0),
584 GATE_CFG(GATE_WWDG2, RCC_WWDG2CFGR, 1, 0),
585 GATE_CFG(GATE_VREF, RCC_VREFCFGR, 1, 0),
586 GATE_CFG(GATE_DTS, RCC_DTSCFGR, 1, 0),
587 GATE_CFG(GATE_CRC, RCC_CRCCFGR, 1, 0),
588 GATE_CFG(GATE_SERC, RCC_SERCCFGR, 1, 0),
589 GATE_CFG(GATE_OSPIIOM, RCC_OSPIIOMCFGR, 1, 0),
590 GATE_CFG(GATE_GICV2M, RCC_GICV2MCFGR, 1, 0),
591 GATE_CFG(GATE_I3C1, RCC_I3C1CFGR, 1, 0),
592 GATE_CFG(GATE_I3C2, RCC_I3C2CFGR, 1, 0),
593 GATE_CFG(GATE_I3C3, RCC_I3C3CFGR, 1, 0),
594 GATE_CFG(GATE_I3C4, RCC_I3C4CFGR, 1, 0),
595 };
596
597 /*
598 * MUX CONFIG
599 */
600
601 #define _MUX_CFG(_id, _offset, _shift, _width, _rdy)\
602 [(_id)] = {\
603 .offset = (_offset),\
604 .shift = (_shift),\
605 .width = (_width),\
606 .ready = (_rdy),\
607 }
608
609 static const struct mux_cfg parent_mp25[MUX_NB] = {
610 _MUX_CFG(MUX_MUXSEL0, RCC_MUXSELCFGR, 0, 2, GATE_PLL4_CKREFST),
611 _MUX_CFG(MUX_MUXSEL1, RCC_MUXSELCFGR, 4, 2, GATE_PLL5_CKREFST),
612 _MUX_CFG(MUX_MUXSEL2, RCC_MUXSELCFGR, 8, 2, GATE_PLL6_CKREFST),
613 _MUX_CFG(MUX_MUXSEL3, RCC_MUXSELCFGR, 12, 2, GATE_PLL7_CKREFST),
614 _MUX_CFG(MUX_MUXSEL4, RCC_MUXSELCFGR, 16, 2, GATE_PLL8_CKREFST),
615 _MUX_CFG(MUX_MUXSEL5, RCC_MUXSELCFGR, 20, 2, MUX_NO_RDY),
616 _MUX_CFG(MUX_MUXSEL6, RCC_MUXSELCFGR, 24, 2, MUX_NO_RDY),
617 _MUX_CFG(MUX_MUXSEL7, RCC_MUXSELCFGR, 28, 2, MUX_NO_RDY),
618 _MUX_CFG(MUX_XBARSEL, RCC_XBAR0CFGR, 0, 4, MUX_NO_RDY),
619 _MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2, MUX_NO_RDY),
620 _MUX_CFG(MUX_D3PER, RCC_D3DCR, 16, 2, MUX_NO_RDY),
621 _MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 1, MUX_NO_RDY),
622 _MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 1, MUX_NO_RDY),
623 _MUX_CFG(MUX_ADC12, RCC_ADC12CFGR, 12, 1, MUX_NO_RDY),
624 _MUX_CFG(MUX_ADC3, RCC_ADC3CFGR, 12, 2, MUX_NO_RDY),
625 _MUX_CFG(MUX_USB2PHY1, RCC_USB2PHY1CFGR, 15, 1, MUX_NO_RDY),
626 _MUX_CFG(MUX_USB2PHY2, RCC_USB2PHY2CFGR, 15, 1, MUX_NO_RDY),
627 _MUX_CFG(MUX_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 15, 1, MUX_NO_RDY),
628 _MUX_CFG(MUX_DSIBLANE, RCC_DSICFGR, 12, 1, MUX_NO_RDY),
629 _MUX_CFG(MUX_DSIPHY, RCC_DSICFGR, 15, 1, MUX_NO_RDY),
630 _MUX_CFG(MUX_LVDSPHY, RCC_LVDSCFGR, 15, 1, MUX_NO_RDY),
631 _MUX_CFG(MUX_DTS, RCC_DTSCFGR, 12, 2, MUX_NO_RDY),
632 };
633
634 /*
635 * DIV CONFIG
636 */
637
638 static const struct div_table_cfg apb_div_table[] = {
639 { .val = 0, .div = 1 },
640 { .val = 1, .div = 2 },
641 { .val = 2, .div = 4 },
642 { .val = 3, .div = 8 },
643 { .val = 4, .div = 16 },
644 { .val = 5, .div = 16 },
645 { .val = 6, .div = 16 },
646 { .val = 7, .div = 16 },
647 /* .div = 0 termination cell */
648 { }
649 };
650
651 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\
652 [(_id)] = {\
653 .offset = (_offset),\
654 .shift = (_shift),\
655 .width = (_width),\
656 .flags = (_flags),\
657 .table = (_table),\
658 .ready = (_ready),\
659 }
660
661 static const struct div_cfg dividers_mp25[DIV_NB] = {
662 _DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_RDY),
663 _DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table,
664 GATE_APB1DIV_RDY),
665 _DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table,
666 GATE_APB2DIV_RDY),
667 _DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table,
668 GATE_APB3DIV_RDY),
669 _DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table,
670 GATE_APB4DIV_RDY),
671 _DIV_CFG(DIV_APBDBG, RCC_APBDBGDIVR, 0, 3, 0, apb_div_table,
672 GATE_APBDBGDIV_RDY),
673 _DIV_CFG(DIV_LSMCU, RCC_LSMCUDIVR, 0, 1, 0, NULL, GATE_LSMCUDIV_RDY),
674 };
675
676 enum stm32_osc {
677 OSC_HSI,
678 OSC_HSE,
679 OSC_MSI,
680 OSC_LSI,
681 OSC_LSE,
682 NB_OSCILLATOR
683 };
684
685 struct clk_stm32_bypass {
686 uint16_t offset;
687 uint8_t bit_byp;
688 uint8_t bit_digbyp;
689 };
690
691 struct clk_stm32_css {
692 uint16_t offset;
693 uint8_t bit_css;
694 };
695
696 struct clk_stm32_drive {
697 uint16_t offset;
698 uint8_t drv_shift;
699 uint8_t drv_width;
700 uint8_t drv_default;
701 };
702
703 struct clk_oscillator_data {
704 const char *name;
705 unsigned long frequency;
706 uint16_t gate_id;
707 struct clk_stm32_bypass *bypass;
708 struct clk_stm32_css *css;
709 struct clk_stm32_drive *drive;
710 };
711
712 #define BYPASS(_offset, _bit_byp, _bit_digbyp) \
713 (&(struct clk_stm32_bypass){\
714 .offset = (_offset),\
715 .bit_byp = (_bit_byp),\
716 .bit_digbyp = (_bit_digbyp),\
717 })
718
719 #define CSS(_offset, _bit_css) \
720 (&(struct clk_stm32_css){\
721 .offset = (_offset),\
722 .bit_css = (_bit_css),\
723 })
724
725 #define DRIVE(_offset, _shift, _width, _default) \
726 (&(struct clk_stm32_drive){\
727 .offset = (_offset),\
728 .drv_shift = (_shift),\
729 .drv_width = (_width),\
730 .drv_default = (_default),\
731 })
732
733 #define OSCILLATOR(idx_osc, _name, _gate_id, _bypass, _css, _drive) \
734 [(idx_osc)] = (struct clk_oscillator_data){\
735 .name = (_name),\
736 .gate_id = (_gate_id),\
737 .bypass = (_bypass),\
738 .css = (_css),\
739 .drive = (_drive),\
740 }
741
742 static struct clk_oscillator_data stm32mp25_osc_data[NB_OSCILLATOR] = {
743 OSCILLATOR(OSC_HSI, "clk-hsi", GATE_HSI,
744 NULL, NULL, NULL),
745
746 OSCILLATOR(OSC_LSI, "clk-lsi", GATE_LSI,
747 NULL, NULL, NULL),
748
749 OSCILLATOR(OSC_MSI, "clk-msi", GATE_MSI,
750 NULL, NULL, NULL),
751
752 OSCILLATOR(OSC_LSE, "clk-lse", GATE_LSE,
753 BYPASS(RCC_BDCR, RCC_BDCR_LSEBYP_BIT,
754 RCC_BDCR_LSEDIGBYP_BIT),
755 CSS(RCC_BDCR, RCC_BDCR_LSECSSON_BIT),
756 DRIVE(RCC_BDCR, RCC_BDCR_LSEDRV_SHIFT,
757 RCC_BDCR_LSEDRV_WIDTH, LSEDRV_MEDIUM_HIGH)),
758
759 OSCILLATOR(OSC_HSE, "clk-hse", GATE_HSE,
760 BYPASS(RCC_OCENSETR, RCC_OCENSETR_HSEBYP_BIT,
761 RCC_OCENSETR_HSEDIGBYP_BIT),
762 CSS(RCC_OCENSETR, RCC_OCENSETR_HSECSSON_BIT),
763 NULL),
764 };
765
clk_oscillator_get_data(unsigned int osc_id)766 static struct clk_oscillator_data *clk_oscillator_get_data(unsigned int osc_id)
767 {
768 assert(osc_id < ARRAY_SIZE(stm32mp25_osc_data));
769
770 return &stm32mp25_osc_data[osc_id];
771 }
772
clk_stm32_get_rate_oscillator(unsigned int osc_id)773 static unsigned long clk_stm32_get_rate_oscillator(unsigned int osc_id)
774 {
775 struct clk_stm32_priv *priv = clk_stm32_get_priv();
776 struct stm32_clk_platdata *pdata = priv->pdata;
777 struct stm32_osci_dt_cfg *osci = &pdata->osci[osc_id];
778
779 return osci->freq;
780 }
781
clk_stm32_pll_get_oscillator_rate(unsigned int sel)782 static unsigned long clk_stm32_pll_get_oscillator_rate(unsigned int sel)
783 {
784 unsigned int osc[] = { OSC_HSI, OSC_HSE, OSC_MSI };
785
786 assert(sel < ARRAY_SIZE(osc));
787
788 return clk_stm32_get_rate_oscillator(osc[sel]);
789 }
790
clk_oscillator_set_bypass(struct clk_stm32_priv * priv,struct clk_oscillator_data * osc_data,bool digbyp,bool bypass)791 static void clk_oscillator_set_bypass(struct clk_stm32_priv *priv,
792 struct clk_oscillator_data *osc_data,
793 bool digbyp, bool bypass)
794 {
795 struct clk_stm32_bypass *bypass_data = osc_data->bypass;
796 uintptr_t address = 0;
797
798 if (!bypass_data)
799 return;
800
801 address = priv->base + bypass_data->offset;
802
803 if (digbyp)
804 io_setbits32(address, BIT(bypass_data->bit_digbyp));
805
806 if (bypass || digbyp)
807 io_setbits32(address, BIT(bypass_data->bit_byp));
808 }
809
clk_oscillator_set_css(struct clk_stm32_priv * priv,struct clk_oscillator_data * osc_data,bool css)810 static void clk_oscillator_set_css(struct clk_stm32_priv *priv,
811 struct clk_oscillator_data *osc_data,
812 bool css)
813 {
814 struct clk_stm32_css *css_data = osc_data->css;
815
816 if (css_data && css)
817 io_setbits32(priv->base + css_data->offset,
818 BIT(css_data->bit_css));
819 }
820
clk_oscillator_set_drive(struct clk_stm32_priv * priv,struct clk_oscillator_data * osc_data,uint8_t lsedrv)821 static void clk_oscillator_set_drive(struct clk_stm32_priv *priv,
822 struct clk_oscillator_data *osc_data,
823 uint8_t lsedrv)
824 {
825 struct clk_stm32_drive *drive_data = osc_data->drive;
826 uintptr_t address = 0;
827 uint32_t mask = 0;
828 uint32_t value = 0;
829
830 if (!drive_data)
831 return;
832
833 address = priv->base + drive_data->offset;
834
835 mask = SHIFT_U32(BIT(drive_data->drv_width) - 1, drive_data->drv_shift);
836
837 /*
838 * Warning: not recommended to switch directly from "high drive"
839 * to "medium low drive", and vice-versa.
840 */
841 value = (io_read32(address) & mask) >> drive_data->drv_shift;
842
843 while (value != lsedrv) {
844 if (value > lsedrv)
845 value--;
846 else
847 value++;
848
849 io_clrsetbits32(address, mask,
850 SHIFT_U32(value, drive_data->drv_shift));
851 }
852 }
853
stm32_enable_oscillator_hse(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)854 static void stm32_enable_oscillator_hse(struct clk_stm32_priv *priv,
855 struct stm32_clk_platdata *pdata)
856 {
857 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_HSE);
858 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE];
859
860 if (!osci->freq)
861 return;
862
863 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass);
864
865 /* Enable clock and wait ready bit */
866 if (stm32_gate_rdy_enable(osc_data->gate_id))
867 panic("timeout to enable hse clock");
868
869 clk_oscillator_set_css(priv, osc_data, osci->css);
870 }
871
stm32_enable_oscillator_lse(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)872 static void stm32_enable_oscillator_lse(struct clk_stm32_priv *priv,
873 struct stm32_clk_platdata *pdata)
874 {
875 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE);
876 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
877
878 if (!osci->freq)
879 return;
880
881 if (stm32_gate_is_enabled(osc_data->gate_id))
882 return;
883
884 clk_oscillator_set_bypass(priv, osc_data, osci->digbyp, osci->bypass);
885
886 clk_oscillator_set_drive(priv, osc_data, osci->drive);
887
888 /* Enable LSE clock, but don't wait ready bit */
889 stm32_gate_enable(osc_data->gate_id);
890 }
891
stm32_enable_oscillator_lsi(struct clk_stm32_priv * priv __unused,struct stm32_clk_platdata * pdata)892 static void stm32_enable_oscillator_lsi(struct clk_stm32_priv *priv __unused,
893 struct stm32_clk_platdata *pdata)
894 {
895 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSI);
896 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSI];
897
898 if (!osci->freq)
899 return;
900
901 /* Enable clock and wait ready bit */
902 if (stm32_gate_rdy_enable(osc_data->gate_id))
903 panic("timeout to enable lsi clock");
904 }
905
clk_stm32_osc_msi_set_rate(struct clk_stm32_priv * priv,unsigned long rate)906 static TEE_Result clk_stm32_osc_msi_set_rate(struct clk_stm32_priv *priv,
907 unsigned long rate)
908 {
909 uintptr_t address = priv->base + RCC_BDCR;
910 uint32_t mask = RCC_BDCR_MSIFREQSEL;
911
912 switch (rate) {
913 case RCC_4_MHZ:
914 io_clrbits32_stm32shregs(address, mask);
915 break;
916 case RCC_16_MHZ:
917 io_setbits32_stm32shregs(address, mask);
918 break;
919 default:
920 return TEE_ERROR_GENERIC;
921 }
922
923 return TEE_SUCCESS;
924 }
925
stm32_enable_oscillator_msi(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)926 static void stm32_enable_oscillator_msi(struct clk_stm32_priv *priv,
927 struct stm32_clk_platdata *pdata)
928 {
929 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_MSI);
930 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_MSI];
931
932 if (!osci->freq)
933 return;
934
935 if (clk_stm32_osc_msi_set_rate(priv, osci->freq) != TEE_SUCCESS) {
936 EMSG("invalid rate %ld Hz for MSI ! (4000000 or 16000000 only)",
937 osci->freq);
938 panic();
939 }
940
941 /* Enable clock and wait ready bit */
942 if (stm32_gate_rdy_enable(osc_data->gate_id))
943 panic("timeout to enable msi clock");
944 }
945
stm32_clk_oscillators_lse_set_css(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)946 static void stm32_clk_oscillators_lse_set_css(struct clk_stm32_priv *priv,
947 struct stm32_clk_platdata *pdata)
948
949 {
950 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE);
951 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
952
953 clk_oscillator_set_css(priv, osc_data, osci->css);
954 }
955
956 static int
stm32_clk_oscillators_wait_lse_ready(struct clk_stm32_priv * priv __unused,struct stm32_clk_platdata * pdata)957 stm32_clk_oscillators_wait_lse_ready(struct clk_stm32_priv *priv __unused,
958 struct stm32_clk_platdata *pdata)
959 {
960 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(OSC_LSE);
961 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE];
962 int ret = 0;
963
964 if (osci->freq && stm32_gate_wait_ready(osc_data->gate_id, true))
965 ret = -1;
966
967 return ret;
968 }
969
stm32_clk_oscillators_enable(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)970 static void stm32_clk_oscillators_enable(struct clk_stm32_priv *priv,
971 struct stm32_clk_platdata *pdata)
972 {
973 stm32_enable_oscillator_hse(priv, pdata);
974 stm32_enable_oscillator_lse(priv, pdata);
975 stm32_enable_oscillator_lsi(priv, pdata);
976 stm32_enable_oscillator_msi(priv, pdata);
977 }
978
979 enum stm32_pll_id {
980 PLL1_ID,
981 PLL2_ID,
982 PLL3_ID,
983 PLL4_ID,
984 PLL5_ID,
985 PLL6_ID,
986 PLL7_ID,
987 PLL8_ID,
988 PLL_NB
989 };
990
991 /* PLL configuration registers offsets from RCC_PLLxCFGR1 */
992 #define RCC_OFFSET_PLLXCFGR1 0x00
993 #define RCC_OFFSET_PLLXCFGR2 0x04
994 #define RCC_OFFSET_PLLXCFGR3 0x08
995 #define RCC_OFFSET_PLLXCFGR4 0x0C
996 #define RCC_OFFSET_PLLXCFGR5 0x10
997 #define RCC_OFFSET_PLLXCFGR6 0x18
998 #define RCC_OFFSET_PLLXCFGR7 0x1C
999
1000 struct stm32_clk_pll {
1001 uint16_t gate_id;
1002 uint16_t mux_id;
1003 uint16_t reg_pllxcfgr1;
1004 };
1005
1006 #define CLK_PLL_CFG(_idx, _gate_id, _mux_id, _reg)\
1007 [(_idx)] = {\
1008 .gate_id = (_gate_id),\
1009 .mux_id = (_mux_id),\
1010 .reg_pllxcfgr1 = (_reg),\
1011 }
1012
1013 static const struct stm32_clk_pll stm32mp25_clk_pll[PLL_NB] = {
1014 CLK_PLL_CFG(PLL1_ID, GATE_PLL1, MUX_MUXSEL5, 0),
1015 CLK_PLL_CFG(PLL2_ID, GATE_PLL2, MUX_MUXSEL6, RCC_PLL2CFGR1),
1016 CLK_PLL_CFG(PLL3_ID, GATE_PLL3, MUX_MUXSEL7, RCC_PLL3CFGR1),
1017 CLK_PLL_CFG(PLL4_ID, GATE_PLL4, MUX_MUXSEL0, RCC_PLL4CFGR1),
1018 CLK_PLL_CFG(PLL5_ID, GATE_PLL5, MUX_MUXSEL1, RCC_PLL5CFGR1),
1019 CLK_PLL_CFG(PLL6_ID, GATE_PLL6, MUX_MUXSEL2, RCC_PLL6CFGR1),
1020 CLK_PLL_CFG(PLL7_ID, GATE_PLL7, MUX_MUXSEL3, RCC_PLL7CFGR1),
1021 CLK_PLL_CFG(PLL8_ID, GATE_PLL8, MUX_MUXSEL4, RCC_PLL8CFGR1),
1022 };
1023
clk_stm32_pll_data(unsigned int idx)1024 static const struct stm32_clk_pll *clk_stm32_pll_data(unsigned int idx)
1025 {
1026 assert(idx < ARRAY_SIZE(stm32mp25_clk_pll));
1027
1028 return &stm32mp25_clk_pll[idx];
1029 }
1030
stm32_clk_parse_oscillator_fdt(const void * fdt,int node,const char * name,struct stm32_osci_dt_cfg * osci)1031 static int stm32_clk_parse_oscillator_fdt(const void *fdt, int node,
1032 const char *name,
1033 struct stm32_osci_dt_cfg *osci)
1034 {
1035 int subnode = 0;
1036
1037 /* default value when oscillator is not found */
1038 osci->freq = 0;
1039
1040 fdt_for_each_subnode(subnode, fdt, node) {
1041 const char *cchar = NULL;
1042 const fdt32_t *cuint = NULL;
1043 int ret = 0;
1044
1045 cchar = fdt_get_name(fdt, subnode, &ret);
1046 if (!cchar)
1047 return -1;
1048
1049 if (strncmp(cchar, name, (size_t)ret))
1050 continue;
1051
1052 if (fdt_get_status(fdt, subnode) == DT_STATUS_DISABLED)
1053 return 0;
1054
1055 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret);
1056 if (!cuint)
1057 return -1;
1058
1059 osci->freq = fdt32_to_cpu(*cuint);
1060
1061 if (fdt_getprop(fdt, subnode, "st,bypass", NULL))
1062 osci->bypass = true;
1063
1064 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL))
1065 osci->digbyp = true;
1066
1067 if (fdt_getprop(fdt, subnode, "st,css", NULL))
1068 osci->css = true;
1069
1070 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive",
1071 LSEDRV_MEDIUM_HIGH);
1072
1073 return 0;
1074 }
1075
1076 return 0;
1077 }
1078
stm32_clk_get_oscillator_name(enum stm32_osc id)1079 static const char *stm32_clk_get_oscillator_name(enum stm32_osc id)
1080 {
1081 if (id < NB_OSCILLATOR)
1082 return stm32mp25_osc_data[id].name;
1083
1084 return NULL;
1085 }
1086
stm32_clk_parse_fdt_all_oscillator(const void * fdt,int node __unused,struct stm32_clk_platdata * pdata)1087 static int stm32_clk_parse_fdt_all_oscillator(const void *fdt,
1088 int node __unused,
1089 struct stm32_clk_platdata *pdata)
1090 {
1091 int fdt_err = 0;
1092 size_t i = 0;
1093 int osc_node = 0;
1094
1095 osc_node = fdt_path_offset(fdt, "/clocks");
1096 if (osc_node < 0)
1097 return -FDT_ERR_NOTFOUND;
1098
1099 for (i = 0; i < pdata->nosci; i++) {
1100 const char *name = NULL;
1101
1102 name = stm32_clk_get_oscillator_name((enum stm32_osc)i);
1103 if (!name)
1104 continue;
1105
1106 fdt_err = stm32_clk_parse_oscillator_fdt(fdt, osc_node, name,
1107 &pdata->osci[i]);
1108 if (fdt_err < 0)
1109 panic();
1110 }
1111
1112 return 0;
1113 }
1114
clk_stm32_parse_pll_fdt(const void * fdt,int subnode,struct stm32_pll_dt_cfg * pll)1115 static int clk_stm32_parse_pll_fdt(const void *fdt, int subnode,
1116 struct stm32_pll_dt_cfg *pll)
1117 {
1118 const fdt32_t *cuint = NULL;
1119 int subnode_pll = 0;
1120 int err = 0;
1121
1122 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL);
1123 if (!cuint)
1124 return 0;
1125
1126 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint));
1127 if (subnode_pll < 0)
1128 return -FDT_ERR_NOTFOUND;
1129
1130 if (fdt_read_uint32_array(fdt, subnode_pll, "cfg", pll->cfg, PLLCFG_NB))
1131 panic("cfg property is mandatory");
1132
1133 err = fdt_read_uint32_array(fdt, subnode_pll, "csg", pll->csg,
1134 PLLCSG_NB);
1135
1136 pll->csg_enabled = (err == 0);
1137
1138 if (err == -FDT_ERR_NOTFOUND)
1139 err = 0;
1140
1141 if (err)
1142 return err;
1143
1144 pll->enabled = true;
1145
1146 pll->frac = fdt_read_uint32_default(fdt, subnode_pll, "frac", 0);
1147
1148 if (fdt_read_uint32(fdt, subnode_pll, "src", &pll->src))
1149 panic("src property is mandatory");
1150
1151 return 0;
1152 }
1153
1154 #define RCC_PLL_NAME_SIZE 20
1155
stm32_clk_parse_fdt_all_pll(const void * fdt,int node,struct stm32_clk_platdata * pdata)1156 static int stm32_clk_parse_fdt_all_pll(const void *fdt, int node,
1157 struct stm32_clk_platdata *pdata)
1158 {
1159 unsigned int i = 0;
1160
1161 for (i = 0; i < pdata->npll; i++) {
1162 struct stm32_pll_dt_cfg *pll = pdata->pll + i;
1163 char name[RCC_PLL_NAME_SIZE] = { };
1164 int subnode = 0;
1165
1166 snprintf(name, sizeof(name), "st,pll-%u", i + 1);
1167
1168 subnode = fdt_subnode_offset(fdt, node, name);
1169 if (subnode < 0)
1170 continue;
1171
1172 if (clk_stm32_parse_pll_fdt(fdt, subnode, pll))
1173 panic();
1174 }
1175
1176 return 0;
1177 }
1178
stm32_clk_parse_fdt_opp(const void * fdt,int node,const char * opp_name,struct stm32_clk_opp_cfg * opp_cfg)1179 static int stm32_clk_parse_fdt_opp(const void *fdt, int node,
1180 const char *opp_name,
1181 struct stm32_clk_opp_cfg *opp_cfg)
1182 {
1183 int subnode = 0;
1184 int nb_opp = 0;
1185 int ret = 0;
1186
1187 node = fdt_subnode_offset(fdt, node, opp_name);
1188 if (node == -FDT_ERR_NOTFOUND)
1189 return 0;
1190
1191 if (node < 0)
1192 return node;
1193
1194 fdt_for_each_subnode(subnode, fdt, node) {
1195 assert(nb_opp <= MAX_OPP);
1196
1197 if (fdt_read_uint32(fdt, subnode, "hz", &opp_cfg->frq))
1198 panic("hz property is mandatory");
1199
1200 if (fdt_read_uint32(fdt, subnode, "st,clksrc", &opp_cfg->src))
1201 panic("st,clksrc property is mandatory");
1202
1203 ret = clk_stm32_parse_pll_fdt(fdt, subnode, &opp_cfg->pll_cfg);
1204 if (ret < 0)
1205 return ret;
1206
1207 opp_cfg++;
1208 nb_opp++;
1209 }
1210
1211 return 0;
1212 }
1213
stm32_clk_parse_fdt_all_opp(const void * fdt,int node,struct stm32_clk_platdata * pdata)1214 static int stm32_clk_parse_fdt_all_opp(const void *fdt, int node,
1215 struct stm32_clk_platdata *pdata)
1216 {
1217 struct stm32_clk_opp_dt_cfg *opp = pdata->opp;
1218
1219 node = fdt_subnode_offset(fdt, node, "st,clk_opp");
1220 if (node == -FDT_ERR_NOTFOUND)
1221 return 0;
1222
1223 if (node < 0)
1224 return node;
1225
1226 return stm32_clk_parse_fdt_opp(fdt, node, "st,ck_cpu1", opp->cpu1_opp);
1227 }
1228
stm32_clk_parse_fdt(const void * fdt,int node,struct stm32_clk_platdata * pdata)1229 static int stm32_clk_parse_fdt(const void *fdt, int node,
1230 struct stm32_clk_platdata *pdata)
1231 {
1232 const fdt32_t *cuint = NULL;
1233 unsigned int i = 0;
1234 int lenp = 0;
1235 int err = 0;
1236
1237 err = stm32_clk_parse_fdt_all_oscillator(fdt, node, pdata);
1238 if (err)
1239 return err;
1240
1241 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata);
1242 if (err)
1243 return err;
1244
1245 err = stm32_clk_parse_fdt_all_opp(fdt, node, pdata);
1246 if (err)
1247 return err;
1248
1249 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,busclk",
1250 pdata->busclk,
1251 &pdata->nbusclk);
1252 if (err)
1253 return err;
1254
1255 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,flexgen",
1256 pdata->flexgen,
1257 &pdata->nflexgen);
1258 if (err)
1259 return err;
1260
1261 err = clk_stm32_parse_fdt_by_name(fdt, node, "st,kerclk",
1262 pdata->kernelclk,
1263 &pdata->nkernelclk);
1264 if (err)
1265 return err;
1266
1267 pdata->c1msrd = fdt_read_uint32_default(fdt, node, "st,c1msrd", 0);
1268
1269 if (fdt_getprop(fdt, node, "st,safe_rst", NULL))
1270 pdata->safe_rst = true;
1271
1272 pdata->rcc_base = stm32_rcc_base();
1273
1274 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp);
1275 if (lenp < 0) {
1276 if (lenp != -FDT_ERR_NOTFOUND)
1277 return lenp;
1278
1279 lenp = 0;
1280 DMSG("No RIF configuration available");
1281 }
1282
1283 pdata->nb_res = (unsigned int)(lenp / sizeof(uint32_t));
1284
1285 assert(pdata->nb_res <= RCC_NB_RIF_RES);
1286
1287 pdata->conf_data.cid_confs = calloc(RCC_NB_RIF_RES, sizeof(uint32_t));
1288 pdata->conf_data.sec_conf = calloc(RCC_NB_CONFS, sizeof(uint32_t));
1289 pdata->conf_data.priv_conf = calloc(RCC_NB_CONFS, sizeof(uint32_t));
1290 pdata->conf_data.lock_conf = calloc(RCC_NB_CONFS, sizeof(uint32_t));
1291 pdata->conf_data.access_mask = calloc(RCC_NB_CONFS, sizeof(uint32_t));
1292 if (!pdata->conf_data.cid_confs || !pdata->conf_data.sec_conf ||
1293 !pdata->conf_data.priv_conf || !pdata->conf_data.access_mask ||
1294 !pdata->conf_data.lock_conf)
1295 panic("Missing memory capacity for RCC RIF configuration");
1296
1297 for (i = 0; i < pdata->nb_res; i++)
1298 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), &pdata->conf_data,
1299 RCC_NB_RIF_RES);
1300
1301 return 0;
1302 }
1303
stm32mp2_a35_ss_on_bypass(void)1304 static void stm32mp2_a35_ss_on_bypass(void)
1305 {
1306 uint64_t timeout = 0;
1307 uint32_t chgclkreq = stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ);
1308
1309 if (chgclkreq & CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) {
1310 /* Nothing to do, clock source is already set on bypass clock */
1311 return;
1312 }
1313
1314 /*
1315 * for clkext2f frequency at 400MHZ, the default flexgen63 config,
1316 * divider by 2 is required with ARM_DIVSEL=0
1317 */
1318 if (chgclkreq & CA35SS_SSC_CHGCLKREQ_ARM_DIVSEL) {
1319 stm32mp_syscfg_write(CA35SS_SSC_CHGCLKREQ,
1320 0U,
1321 CA35SS_SSC_CHGCLKREQ_ARM_DIVSEL);
1322 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1323 while (!timeout_elapsed(timeout))
1324 if (!(stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1325 CA35SS_SSC_CHGCLKREQ_ARM_DIVSELACK))
1326 break;
1327 if (stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1328 CA35SS_SSC_CHGCLKREQ_ARM_DIVSELACK)
1329 panic("Cannot set div on A35 bypass clock");
1330 }
1331
1332 stm32mp_syscfg_write(CA35SS_SSC_CHGCLKREQ,
1333 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ,
1334 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK);
1335
1336 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1337 while (!timeout_elapsed(timeout))
1338 if (stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1339 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK)
1340 break;
1341
1342 if (!(stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1343 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK))
1344 panic("Cannot switch A35 to bypass clock");
1345
1346 stm32mp_syscfg_write(CA35SS_SSC_PLL_EN,
1347 0,
1348 CA35SS_SSC_PLL_EN_NRESET_SWPLL_MASK);
1349 }
1350
stm32mp2_clk_xbar_on_hsi(struct clk_stm32_priv * priv)1351 static void stm32mp2_clk_xbar_on_hsi(struct clk_stm32_priv *priv)
1352 {
1353 uintptr_t xbar0cfgr = priv->base + RCC_XBAR0CFGR;
1354 uint32_t i = 0;
1355
1356 for (i = 0; i < XBAR_ROOT_CHANNEL_NB; i++)
1357 io_clrsetbits32(xbar0cfgr + (0x4 * i),
1358 RCC_XBAR0CFGR_XBAR0SEL_MASK, XBAR_SRC_HSI);
1359 }
1360
stm32mp2_a35_pll1_start(void)1361 static int stm32mp2_a35_pll1_start(void)
1362 {
1363 uint64_t timeout = 0;
1364
1365 stm32mp_syscfg_write(CA35SS_SSC_PLL_EN,
1366 CA35SS_SSC_PLL_EN_PLL_EN,
1367 CA35SS_SSC_PLL_EN_PLL_EN);
1368
1369 /* Wait PLL lock */
1370 timeout = timeout_init_us(PLLRDY_TIMEOUT);
1371 while (!timeout_elapsed(timeout))
1372 if (stm32mp_syscfg_read(CA35SS_SSC_PLL_EN) &
1373 CA35SS_SSC_PLL_EN_LOCKP_MASK)
1374 break;
1375
1376 if (!(stm32mp_syscfg_read(CA35SS_SSC_PLL_EN) &
1377 CA35SS_SSC_PLL_EN_LOCKP_MASK)) {
1378 EMSG("PLL1 not locked");
1379 return -1;
1380 }
1381
1382 /* De-assert reset on PLL output clock path */
1383 stm32mp_syscfg_write(CA35SS_SSC_PLL_EN,
1384 CA35SS_SSC_PLL_EN_NRESET_SWPLL,
1385 CA35SS_SSC_PLL_EN_NRESET_SWPLL_MASK);
1386
1387 /* Switch CPU clock to PLL clock */
1388 stm32mp_syscfg_write(CA35SS_SSC_CHGCLKREQ,
1389 0,
1390 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKREQ_MASK);
1391
1392 /* Wait for clock change acknowledge */
1393 timeout = timeout_init_us(CLKSRC_TIMEOUT);
1394 while (!timeout_elapsed(timeout))
1395 if (!(stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1396 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK))
1397 break;
1398
1399 if (stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ) &
1400 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) {
1401 EMSG("A35 switch to PLL1 failed");
1402 return -1;
1403 }
1404
1405 return 0;
1406 }
1407
stm32mp2_a35_pll1_config(uint32_t fbdiv,uint32_t refdiv,uint32_t postdiv1,uint32_t postdiv2)1408 static void stm32mp2_a35_pll1_config(uint32_t fbdiv, uint32_t refdiv,
1409 uint32_t postdiv1, uint32_t postdiv2)
1410 {
1411 stm32mp_syscfg_write(CA35SS_SSC_PLL_FREQ1,
1412 SHIFT_U32(refdiv,
1413 CA35SS_SSC_PLL_FREQ1_REFDIV_SHIFT) |
1414 SHIFT_U32(fbdiv, CA35SS_SSC_PLL_FREQ1_FBDIV_SHIFT),
1415 CA35SS_SSC_PLL_FREQ1_MASK);
1416
1417 stm32mp_syscfg_write(CA35SS_SSC_PLL_FREQ2,
1418 SHIFT_U32(postdiv1,
1419 CA35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT) |
1420 SHIFT_U32(postdiv2,
1421 CA35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT),
1422 CA35SS_SSC_PLL_FREQ2_MASK);
1423 }
1424
clk_stm32_pll_config_output(struct clk_stm32_priv * priv,const struct stm32_clk_pll * pll,uint32_t pllsrc,uint32_t * pllcfg,uint32_t fracv)1425 static void clk_stm32_pll_config_output(struct clk_stm32_priv *priv,
1426 const struct stm32_clk_pll *pll,
1427 uint32_t pllsrc,
1428 uint32_t *pllcfg,
1429 uint32_t fracv)
1430 {
1431 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1432 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;
1433 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
1434 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
1435 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;
1436 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;
1437 int sel = (pllsrc & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1438 unsigned long refclk = clk_stm32_pll_get_oscillator_rate(sel);
1439
1440 if (!fracv) {
1441 /* PLL in integer mode */
1442
1443 /*
1444 * No need to check max clock, as oscillator reference clocks
1445 * will always be less than 1.2GHz
1446 */
1447 if (refclk < PLL_REFCLK_MIN)
1448 panic();
1449
1450 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK);
1451 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
1452 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_DACEN);
1453 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
1454 io_setbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);
1455 } else {
1456 /* PLL in frac mode */
1457
1458 /*
1459 * No need to check max clock, as oscillator reference clocks
1460 * will always be less than 1.2GHz
1461 */
1462 if (refclk < PLL_FRAC_REFCLK_MIN)
1463 panic();
1464
1465 io_clrsetbits32(pllxcfgr3, RCC_PLLxCFGR3_FRACIN_MASK,
1466 fracv & RCC_PLLxCFGR3_FRACIN_MASK);
1467 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
1468 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
1469 }
1470
1471 assert(pllcfg[REFDIV]);
1472
1473 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK,
1474 SHIFT_U32(pllcfg[FBDIV], RCC_PLLxCFGR2_FBDIV_SHIFT) &
1475 RCC_PLLxCFGR2_FBDIV_MASK);
1476 io_clrsetbits32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK,
1477 pllcfg[REFDIV] & RCC_PLLxCFGR2_FREFDIV_MASK);
1478 io_clrsetbits32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK,
1479 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK);
1480 io_clrsetbits32(pllxcfgr7, RCC_PLLxCFGR7_POSTDIV2_MASK,
1481 pllcfg[POSTDIV2] & RCC_PLLxCFGR7_POSTDIV2_MASK);
1482
1483 if (!pllcfg[POSTDIV1] || !pllcfg[POSTDIV2]) {
1484 /* Bypass mode */
1485 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS);
1486 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN);
1487 } else {
1488 io_clrbits32(pllxcfgr4, RCC_PLLxCFGR4_BYPASS);
1489 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_FOUTPOSTDIVEN);
1490 }
1491 }
1492
clk_stm32_pll_config_csg(struct clk_stm32_priv * priv,const struct stm32_clk_pll * pll,uint32_t * csg)1493 static void clk_stm32_pll_config_csg(struct clk_stm32_priv *priv,
1494 const struct stm32_clk_pll *pll,
1495 uint32_t *csg)
1496 {
1497 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1498 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
1499 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
1500 uintptr_t pllxcfgr5 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR5;
1501
1502 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK,
1503 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK);
1504 io_clrsetbits32(pllxcfgr5, RCC_PLLxCFGR5_SPREAD_MASK,
1505 SHIFT_U32(csg[SPREAD], RCC_PLLxCFGR5_SPREAD_SHIFT) &
1506 RCC_PLLxCFGR5_SPREAD_MASK);
1507
1508 if (csg[DOWNSPREAD])
1509 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD);
1510 else
1511 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_DOWNSPREAD);
1512
1513 io_clrbits32(pllxcfgr3, RCC_PLLxCFGR3_SSCGDIS);
1514
1515 io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_PLLEN);
1516 udelay(1);
1517
1518 io_setbits32(pllxcfgr4, RCC_PLLxCFGR4_DSMEN);
1519 io_setbits32(pllxcfgr3, RCC_PLLxCFGR3_DACEN);
1520 }
1521
clk_stm32_pll_get_pdata(unsigned int pll_idx)1522 static struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(unsigned int pll_idx)
1523 {
1524 struct clk_stm32_priv *priv = clk_stm32_get_priv();
1525 struct stm32_clk_platdata *pdata = priv->pdata;
1526
1527 assert(pll_idx < pdata->npll);
1528
1529 return &pdata->pll[pll_idx];
1530 }
1531
clk_stm32_pll_set_mux(struct clk_stm32_priv * priv __unused,uint32_t src)1532 static int clk_stm32_pll_set_mux(struct clk_stm32_priv *priv __unused,
1533 uint32_t src)
1534 {
1535 int mux = (src & MUX_ID_MASK) >> MUX_ID_SHIFT;
1536 int sel = (src & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1537
1538 if (stm32_mux_set_parent(mux, sel))
1539 return -1;
1540 else
1541 return 0;
1542
1543 }
1544
clk_stm32_pll1_init(struct clk_stm32_priv * priv,int pll_idx __unused,struct stm32_pll_dt_cfg * pll_conf)1545 static void clk_stm32_pll1_init(struct clk_stm32_priv *priv,
1546 int pll_idx __unused,
1547 struct stm32_pll_dt_cfg *pll_conf)
1548 {
1549 int sel = (pll_conf->src & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1550 unsigned long refclk = 0;
1551
1552 stm32mp2_a35_ss_on_bypass();
1553
1554 if (clk_stm32_pll_set_mux(priv, pll_conf->src))
1555 panic();
1556
1557 refclk = clk_stm32_pll_get_oscillator_rate(sel);
1558
1559 /*
1560 * No need to check max clock, as oscillator reference clocks will
1561 * always be less than 1.2GHz
1562 */
1563 if (refclk < PLL_REFCLK_MIN)
1564 panic();
1565
1566 stm32mp2_a35_pll1_config(pll_conf->cfg[FBDIV],
1567 pll_conf->cfg[REFDIV],
1568 pll_conf->cfg[POSTDIV1],
1569 pll_conf->cfg[POSTDIV2]);
1570
1571 if (stm32mp2_a35_pll1_start())
1572 panic();
1573 }
1574
clk_stm32_pll_init(struct clk_stm32_priv * priv,int pll_idx,struct stm32_pll_dt_cfg * pll_conf)1575 static void clk_stm32_pll_init(struct clk_stm32_priv *priv, int pll_idx,
1576 struct stm32_pll_dt_cfg *pll_conf)
1577 {
1578 const struct stm32_clk_pll *pll = clk_stm32_pll_data(pll_idx);
1579 uintptr_t pllxcfgr1 = priv->base + pll->reg_pllxcfgr1;
1580 bool spread_spectrum = false;
1581
1582 if (stm32_gate_rdy_disable(pll->gate_id))
1583 panic();
1584
1585 if (clk_stm32_pll_set_mux(priv, pll_conf->src))
1586 panic();
1587
1588 clk_stm32_pll_config_output(priv, pll, pll_conf->src,
1589 pll_conf->cfg, pll_conf->frac);
1590
1591 if (pll_conf->csg_enabled) {
1592 clk_stm32_pll_config_csg(priv, pll, pll_conf->csg);
1593 spread_spectrum = true;
1594 }
1595
1596 if (stm32_gate_rdy_enable(pll->gate_id))
1597 panic();
1598
1599 if (spread_spectrum)
1600 io_clrbits32(pllxcfgr1, RCC_PLLxCFGR1_SSMODRST);
1601 }
1602
stm32_clk_pll_configure(struct clk_stm32_priv * priv)1603 static int stm32_clk_pll_configure(struct clk_stm32_priv *priv)
1604 {
1605 struct stm32_pll_dt_cfg *pll_conf = NULL;
1606 size_t i = 0;
1607
1608 for (i = 0; i < PLL_NB; i++) {
1609 pll_conf = clk_stm32_pll_get_pdata(i);
1610
1611 if (pll_conf->enabled) {
1612 /* Skip the PLL3 (need GPU regulator to configure) */
1613 if (i == PLL3_ID)
1614 continue;
1615
1616 /* Skip the PLL2 (reserved to DDR) */
1617 if (i == PLL2_ID)
1618 continue;
1619
1620 if (i == PLL1_ID)
1621 clk_stm32_pll1_init(priv, i, pll_conf);
1622 else
1623 clk_stm32_pll_init(priv, i, pll_conf);
1624 }
1625 }
1626
1627 return 0;
1628 }
1629
1630 #define __WORD_BIT 32
1631
wait_predivsr(uint16_t channel)1632 static int wait_predivsr(uint16_t channel)
1633 {
1634 uintptr_t rcc_base = stm32_rcc_base();
1635 uintptr_t previvsr = 0;
1636 uint32_t channel_bit = 0;
1637 uint32_t value = 0;
1638
1639 if (channel < __WORD_BIT) {
1640 previvsr = rcc_base + RCC_PREDIVSR1;
1641 channel_bit = BIT(channel);
1642 } else {
1643 previvsr = rcc_base + RCC_PREDIVSR2;
1644 channel_bit = BIT(channel - __WORD_BIT);
1645 }
1646
1647 if (IO_READ32_POLL_TIMEOUT(previvsr, value, !(value & channel_bit), 0,
1648 CLKDIV_TIMEOUT)) {
1649 EMSG("Pre divider status: %#"PRIx32, io_read32(previvsr));
1650 return -1;
1651 }
1652
1653 return 0;
1654 }
1655
wait_findivsr(uint16_t channel)1656 static int wait_findivsr(uint16_t channel)
1657 {
1658 uintptr_t rcc_base = stm32_rcc_base();
1659 uintptr_t finvivsr = 0;
1660 uint32_t channel_bit = 0;
1661 uint32_t value = 0;
1662
1663 if (channel < __WORD_BIT) {
1664 finvivsr = rcc_base + RCC_FINDIVSR1;
1665 channel_bit = BIT(channel);
1666 } else {
1667 finvivsr = rcc_base + RCC_FINDIVSR2;
1668 channel_bit = BIT(channel - __WORD_BIT);
1669 }
1670
1671 if (IO_READ32_POLL_TIMEOUT(finvivsr, value, !(value & channel_bit), 0,
1672 CLKDIV_TIMEOUT)) {
1673 EMSG("Final divider status: %#"PRIx32, io_read32(finvivsr));
1674 return -1;
1675 }
1676
1677 return 0;
1678 }
1679
wait_xbar_sts(uint16_t channel)1680 static int wait_xbar_sts(uint16_t channel)
1681 {
1682 uintptr_t rcc_base = stm32_rcc_base();
1683 uintptr_t xbar_cfgr = rcc_base + RCC_XBAR0CFGR + (0x4 * channel);
1684 uint32_t value = 0;
1685
1686 if (IO_READ32_POLL_TIMEOUT(xbar_cfgr, value,
1687 !(value & RCC_XBAR0CFGR_XBAR0STS), 0,
1688 CLKDIV_TIMEOUT)) {
1689 EMSG("XBAR%"PRIu16"CFGR: %#"PRIx32, channel,
1690 io_read32(xbar_cfgr));
1691 return -1;
1692 }
1693
1694 return 0;
1695 }
1696
flexclkgen_search_config(uint16_t channel,unsigned int * clk_src,unsigned int * prediv,unsigned int * findiv)1697 static TEE_Result flexclkgen_search_config(uint16_t channel,
1698 unsigned int *clk_src,
1699 unsigned int *prediv,
1700 unsigned int *findiv)
1701 {
1702 struct clk_stm32_priv *priv = clk_stm32_get_priv();
1703 struct stm32_clk_platdata *pdata = priv->pdata;
1704 unsigned int flex_id = U(0);
1705 uint32_t dt_cfg = U(0);
1706 uint32_t i = U(0);
1707
1708 assert(clk_src && prediv && findiv);
1709
1710 /*
1711 * pdata->flexgen is the array of all the flexgen configuration from
1712 * the device tree.
1713 * The binding does not enforce the description of all flexgen nor
1714 * the order it which they are listed.
1715 */
1716 for (i = 0; i < pdata->nflexgen; i++) {
1717 dt_cfg = pdata->flexgen[i];
1718
1719 flex_id = (dt_cfg & FLEX_ID_MASK) >> FLEX_ID_SHIFT;
1720 if (flex_id == channel) {
1721 *clk_src = (dt_cfg & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT;
1722 *prediv = (dt_cfg & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT;
1723 *findiv = (dt_cfg & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT;
1724
1725 return TEE_SUCCESS;
1726 }
1727 }
1728
1729 return TEE_ERROR_ITEM_NOT_FOUND;
1730 }
1731
flexclkgen_config_channel(uint16_t channel,unsigned int clk_src,unsigned int prediv,unsigned int findiv)1732 static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src,
1733 unsigned int prediv, unsigned int findiv)
1734 {
1735 uintptr_t rcc_base = stm32_rcc_base();
1736
1737 if (wait_predivsr(channel))
1738 panic();
1739
1740 io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel),
1741 RCC_PREDIV0CFGR_PREDIV0_MASK, prediv);
1742
1743 if (wait_predivsr(channel))
1744 panic();
1745
1746 if (wait_findivsr(channel))
1747 panic();
1748
1749 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),
1750 RCC_FINDIV0CFGR_FINDIV0_MASK,
1751 findiv);
1752
1753 if (wait_findivsr(channel))
1754 panic();
1755
1756 if (wait_xbar_sts(channel))
1757 panic();
1758
1759 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel),
1760 RCC_XBAR0CFGR_XBAR0SEL_MASK,
1761 clk_src);
1762
1763 io_setbits32(rcc_base + RCC_XBAR0CFGR + (0x4 * channel),
1764 RCC_XBAR0CFGR_XBAR0EN);
1765
1766 if (wait_xbar_sts(channel))
1767 panic();
1768 }
1769
stm32mp2_clk_flexgen_configure(struct clk_stm32_priv * priv)1770 static int stm32mp2_clk_flexgen_configure(struct clk_stm32_priv *priv)
1771 {
1772 struct stm32_clk_platdata *pdata = priv->pdata;
1773 uint32_t i = 0;
1774
1775 for (i = 0; i < pdata->nflexgen; i++) {
1776 uint32_t val = pdata->flexgen[i];
1777 uint32_t cmd = 0;
1778 uint32_t cmd_data = 0;
1779 unsigned int channel = 0;
1780 unsigned int clk_src = 0;
1781 unsigned int pdiv = 0;
1782 unsigned int fdiv = 0;
1783
1784 cmd = (val & CMD_MASK) >> CMD_SHIFT;
1785 cmd_data = val & ~CMD_MASK;
1786
1787 if (cmd != CMD_FLEXGEN)
1788 continue;
1789
1790 channel = (cmd_data & FLEX_ID_MASK) >> FLEX_ID_SHIFT;
1791
1792 /*
1793 * Skip ck_ker_stgen configuration, will be done by
1794 * stgen driver.
1795 */
1796 if (channel == FLEX_STGEN)
1797 continue;
1798
1799 clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT;
1800 pdiv = (cmd_data & FLEX_PDIV_MASK) >> FLEX_PDIV_SHIFT;
1801 fdiv = (cmd_data & FLEX_FDIV_MASK) >> FLEX_FDIV_SHIFT;
1802
1803 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv);
1804 }
1805
1806 return 0;
1807 }
1808
stm32_clk_configure_div(struct clk_stm32_priv * priv __unused,uint32_t data)1809 static int stm32_clk_configure_div(struct clk_stm32_priv *priv __unused,
1810 uint32_t data)
1811 {
1812 uint32_t div_id = 0;
1813 uint32_t div_n = 0;
1814
1815 div_id = (data & DIV_ID_MASK) >> DIV_ID_SHIFT;
1816 div_n = (data & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT;
1817
1818 return stm32_div_set_value(div_id, div_n);
1819 }
1820
stm32_clk_configure_mux(struct clk_stm32_priv * priv __unused,uint32_t data)1821 static int stm32_clk_configure_mux(struct clk_stm32_priv *priv __unused,
1822 uint32_t data)
1823 {
1824 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT;
1825 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT;
1826
1827 if (stm32_mux_set_parent(mux, sel))
1828 return -1;
1829 else
1830 return 0;
1831 }
1832
stm32_clk_configure_by_addr_val(struct clk_stm32_priv * priv,uint32_t data)1833 static int stm32_clk_configure_by_addr_val(struct clk_stm32_priv *priv,
1834 uint32_t data)
1835 {
1836 uint32_t addr = data >> CLK_ADDR_SHIFT;
1837 uint32_t val = data & CLK_ADDR_VAL_MASK;
1838
1839 io_setbits32(priv->base + addr, val);
1840
1841 return 0;
1842 }
1843
stm32_clk_configure_obs(struct clk_stm32_priv * priv,uint32_t data)1844 static void stm32_clk_configure_obs(struct clk_stm32_priv *priv,
1845 uint32_t data)
1846 {
1847 uint32_t id = (data & OBS_ID_MASK) >> OBS_ID_SHIFT;
1848 uint32_t status = (data & OBS_STATUS_MASK) >> OBS_STATUS_SHIFT;
1849 uint32_t int_ext = (data & OBS_INTEXT_MASK) >> OBS_INTEXT_SHIFT;
1850 uint32_t div = (data & OBS_DIV_MASK) >> OBS_DIV_SHIFT;
1851 uint32_t inv = (data & OBS_INV_MASK) >> OBS_INV_SHIFT;
1852 uint32_t sel = (data & OBS_SEL_MASK) >> OBS_SEL_SHIFT;
1853 uint32_t reg = 0;
1854 uint32_t val = 0;
1855
1856 if (!id)
1857 reg = RCC_FCALCOBS0CFGR;
1858 else
1859 reg = RCC_FCALCOBS1CFGR;
1860
1861 if (status)
1862 val |= RCC_FCALCOBS0CFGR_CKOBSEN;
1863
1864 if (int_ext == OBS_EXT) {
1865 val |= RCC_FCALCOBS0CFGR_CKOBSEXTSEL;
1866 val |= SHIFT_U32(sel, RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT);
1867 } else {
1868 val |= SHIFT_U32(sel, RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT);
1869 }
1870
1871 if (inv)
1872 val |= RCC_FCALCOBS0CFGR_CKOBSINV;
1873
1874 val |= SHIFT_U32(div, RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT);
1875
1876 io_write32(priv->base + reg, val);
1877 }
1878
stm32_clk_configure(struct clk_stm32_priv * priv,uint32_t val)1879 static int stm32_clk_configure(struct clk_stm32_priv *priv, uint32_t val)
1880 {
1881 uint32_t cmd_data = 0;
1882 uint32_t cmd = 0;
1883 int ret = 0;
1884
1885 if (val & CMD_ADDR_BIT) {
1886 cmd_data = val & ~CMD_ADDR_BIT;
1887
1888 return stm32_clk_configure_by_addr_val(priv, cmd_data);
1889 }
1890
1891 cmd = (val & CMD_MASK) >> CMD_SHIFT;
1892 cmd_data = val & ~CMD_MASK;
1893
1894 switch (cmd) {
1895 case CMD_DIV:
1896 ret = stm32_clk_configure_div(priv, cmd_data);
1897 break;
1898
1899 case CMD_MUX:
1900 ret = stm32_clk_configure_mux(priv, cmd_data);
1901 break;
1902
1903 case CMD_OBS:
1904 stm32_clk_configure_obs(priv, cmd_data);
1905 break;
1906
1907 default:
1908 EMSG("cmd unknown ! : %#"PRIx32, val);
1909 ret = -1;
1910 }
1911
1912 return ret;
1913 }
1914
stm32_clk_bus_configure(struct clk_stm32_priv * priv)1915 static int stm32_clk_bus_configure(struct clk_stm32_priv *priv)
1916 {
1917 struct stm32_clk_platdata *pdata = priv->pdata;
1918 uint32_t i = 0;
1919
1920 for (i = 0; i < pdata->nbusclk; i++) {
1921 int ret = 0;
1922
1923 ret = stm32_clk_configure(priv, pdata->busclk[i]);
1924 if (ret)
1925 return ret;
1926 }
1927
1928 return 0;
1929 }
1930
stm32_clk_kernel_configure(struct clk_stm32_priv * priv)1931 static int stm32_clk_kernel_configure(struct clk_stm32_priv *priv)
1932 {
1933 struct stm32_clk_platdata *pdata = priv->pdata;
1934 uint32_t i = 0;
1935
1936 for (i = 0; i < pdata->nkernelclk; i++) {
1937 int ret = 0;
1938
1939 ret = stm32_clk_configure(priv, pdata->kernelclk[i]);
1940 if (ret)
1941 return ret;
1942 }
1943
1944 return 0;
1945 }
1946
stm32mp2_init_clock_tree(struct clk_stm32_priv * priv,struct stm32_clk_platdata * pdata)1947 static void stm32mp2_init_clock_tree(struct clk_stm32_priv *priv,
1948 struct stm32_clk_platdata *pdata)
1949 {
1950 stm32_clk_oscillators_enable(priv, pdata);
1951
1952 /* Come back to HSI for flexgen */
1953 stm32mp2_clk_xbar_on_hsi(priv);
1954
1955 if (stm32_clk_pll_configure(priv))
1956 panic("Cannot configure plls");
1957
1958 /* Wait LSE ready before to use it */
1959 if (stm32_clk_oscillators_wait_lse_ready(priv, pdata))
1960 panic("Timeout: to enable LSE");
1961
1962 if (stm32mp2_clk_flexgen_configure(priv))
1963 panic("Cannot configure flexgen");
1964
1965 if (stm32_clk_bus_configure(priv))
1966 panic("Cannot config bus clocks");
1967
1968 if (stm32_clk_kernel_configure(priv))
1969 panic("Cannot configure kernel clocks");
1970
1971 /* Configure LSE css after RTC source configuration */
1972 stm32_clk_oscillators_lse_set_css(priv, pdata);
1973 }
1974
clk_stm32_osc_enable(struct clk * clk)1975 static TEE_Result clk_stm32_osc_enable(struct clk *clk)
1976 {
1977 return clk_stm32_gate_ready_ops.enable(clk);
1978 }
1979
clk_stm32_osc_disable(struct clk * clk)1980 static void clk_stm32_osc_disable(struct clk *clk)
1981 {
1982 clk_stm32_gate_ready_ops.disable(clk);
1983 }
1984
1985 static const struct clk_ops clk_stm32_osc_ops = {
1986 .enable = clk_stm32_osc_enable,
1987 .disable = clk_stm32_osc_disable,
1988 };
1989
clk_stm32_msi_get_rate(struct clk * clk __unused,unsigned long prate __unused)1990 static unsigned long clk_stm32_msi_get_rate(struct clk *clk __unused,
1991 unsigned long prate __unused)
1992 {
1993 struct clk_stm32_priv *priv = clk_stm32_get_priv();
1994 uintptr_t address = priv->base + RCC_BDCR;
1995
1996 if ((io_read32(address) & RCC_BDCR_MSIFREQSEL))
1997 return RCC_16_MHZ;
1998
1999 return RCC_4_MHZ;
2000 }
2001
clk_stm32_msi_set_rate(struct clk * clk __unused,unsigned long rate,unsigned long prate __unused)2002 static TEE_Result clk_stm32_msi_set_rate(struct clk *clk __unused,
2003 unsigned long rate,
2004 unsigned long prate __unused)
2005 {
2006 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2007
2008 return clk_stm32_osc_msi_set_rate(priv, rate);
2009 }
2010
2011 static const struct clk_ops clk_stm32_oscillator_msi_ops = {
2012 .enable = clk_stm32_osc_enable,
2013 .disable = clk_stm32_osc_disable,
2014 .get_rate = clk_stm32_msi_get_rate,
2015 .set_rate = clk_stm32_msi_set_rate,
2016 };
2017
clk_stm32_hse_div_set_rate(struct clk * clk,unsigned long rate,unsigned long parent_rate)2018 static TEE_Result clk_stm32_hse_div_set_rate(struct clk *clk,
2019 unsigned long rate,
2020 unsigned long parent_rate)
2021 {
2022 return clk_stm32_divider_set_rate(clk, rate, parent_rate);
2023 }
2024
2025 static const struct clk_ops clk_stm32_hse_div_ops = {
2026 .get_rate = clk_stm32_divider_get_rate,
2027 .set_rate = clk_stm32_hse_div_set_rate,
2028 };
2029
clk_stm32_hsediv2_enable(struct clk * clk)2030 static TEE_Result clk_stm32_hsediv2_enable(struct clk *clk)
2031 {
2032 return clk_stm32_gate_ops.enable(clk);
2033 }
2034
clk_stm32_hsediv2_disable(struct clk * clk)2035 static void clk_stm32_hsediv2_disable(struct clk *clk)
2036 {
2037 clk_stm32_gate_ops.disable(clk);
2038 }
2039
clk_stm32_hsediv2_get_rate(struct clk * clk __unused,unsigned long prate)2040 static unsigned long clk_stm32_hsediv2_get_rate(struct clk *clk __unused,
2041 unsigned long prate)
2042 {
2043 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2044 uintptr_t addr = priv->base + RCC_OCENSETR;
2045
2046 if (io_read32(addr) & RCC_OCENSETR_HSEDIV2BYP)
2047 return prate;
2048
2049 return prate / 2;
2050 }
2051
2052 static const struct clk_ops clk_hsediv2_ops = {
2053 .enable = clk_stm32_hsediv2_enable,
2054 .disable = clk_stm32_hsediv2_disable,
2055 .get_rate = clk_stm32_hsediv2_get_rate,
2056 };
2057
2058 struct clk_stm32_pll_cfg {
2059 uint32_t pll_offset;
2060 int gate_id;
2061 int mux_id;
2062 };
2063
clk_get_pll1_fvco_rate(unsigned long refclk)2064 static unsigned long clk_get_pll1_fvco_rate(unsigned long refclk)
2065 {
2066 uint32_t reg = stm32mp_syscfg_read(CA35SS_SSC_PLL_FREQ1);
2067 uint32_t fbdiv = 0;
2068 uint32_t refdiv = 0;
2069 unsigned long freq = 0;
2070
2071 fbdiv = (reg & CA35SS_SSC_PLL_FREQ1_FBDIV_MASK) >>
2072 CA35SS_SSC_PLL_FREQ1_FBDIV_SHIFT;
2073
2074 refdiv = (reg & CA35SS_SSC_PLL_FREQ1_REFDIV_MASK) >>
2075 CA35SS_SSC_PLL_FREQ1_REFDIV_SHIFT;
2076
2077 if (!refdiv || MUL_OVERFLOW(refclk, fbdiv, &freq))
2078 panic();
2079
2080 return freq / refdiv;
2081 }
2082
clk_stm32_pll1_get_rate(struct clk * clk __unused,unsigned long prate)2083 static unsigned long clk_stm32_pll1_get_rate(struct clk *clk __unused,
2084 unsigned long prate)
2085 {
2086 uint32_t reg = stm32mp_syscfg_read(CA35SS_SSC_PLL_FREQ2);
2087 unsigned long dfout = 0;
2088 uint32_t postdiv1 = 0;
2089 uint32_t postdiv2 = 0;
2090
2091 postdiv1 = (reg & CA35SS_SSC_PLL_FREQ2_POSTDIV1_MASK) >>
2092 CA35SS_SSC_PLL_FREQ2_POSTDIV1_SHIFT;
2093
2094 postdiv2 = (reg & CA35SS_SSC_PLL_FREQ2_POSTDIV2_MASK) >>
2095 CA35SS_SSC_PLL_FREQ2_POSTDIV2_SHIFT;
2096
2097 if (!postdiv1 || !postdiv2)
2098 dfout = prate;
2099 else
2100 dfout = clk_get_pll1_fvco_rate(prate) / (postdiv1 * postdiv2);
2101
2102 return dfout;
2103 }
2104
2105 static struct stm32_clk_opp_cfg *
clk_stm32_get_opp_config(struct stm32_clk_opp_cfg * opp_cfg,unsigned long rate)2106 clk_stm32_get_opp_config(struct stm32_clk_opp_cfg *opp_cfg, unsigned long rate)
2107 {
2108 unsigned int i = 0;
2109
2110 for (i = 0; i < MAX_OPP && opp_cfg->frq; i++, opp_cfg++)
2111 if (opp_cfg->frq == rate)
2112 return opp_cfg;
2113
2114 return NULL;
2115 }
2116
clk_stm32_pll1_set_rate(struct clk * clk __unused,unsigned long rate,unsigned long parent_rate __unused)2117 static TEE_Result clk_stm32_pll1_set_rate(struct clk *clk __unused,
2118 unsigned long rate,
2119 unsigned long parent_rate __unused)
2120 {
2121 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2122 struct stm32_clk_platdata *pdata = priv->pdata;
2123 struct stm32_pll_dt_cfg *pll_conf = NULL;
2124 struct stm32_clk_opp_cfg *opp = NULL;
2125
2126 opp = clk_stm32_get_opp_config(pdata->opp->cpu1_opp, rate);
2127 if (!opp)
2128 return TEE_ERROR_GENERIC;
2129
2130 pll_conf = &opp->pll_cfg;
2131
2132 clk_stm32_pll1_init(priv, PLL1_ID, pll_conf);
2133
2134 return TEE_SUCCESS;
2135 }
2136
clk_stm32_pll_get_parent(struct clk * clk)2137 static size_t clk_stm32_pll_get_parent(struct clk *clk)
2138 {
2139 struct clk_stm32_pll_cfg *cfg = clk->priv;
2140
2141 return stm32_mux_get_parent(cfg->mux_id);
2142 }
2143
2144 static const struct clk_ops clk_stm32_pll1_ops = {
2145 .get_parent = clk_stm32_pll_get_parent,
2146 .get_rate = clk_stm32_pll1_get_rate,
2147 .set_rate = clk_stm32_pll1_set_rate,
2148 };
2149
clk_get_pll_fvco(uint32_t offset_base,unsigned long prate)2150 static unsigned long clk_get_pll_fvco(uint32_t offset_base,
2151 unsigned long prate)
2152 {
2153 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2154 uintptr_t pllxcfgr1 = priv->base + offset_base;
2155 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2;
2156 uintptr_t pllxcfgr3 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR3;
2157 unsigned long fvco = 0;
2158 uint32_t fracin = 0;
2159 uint32_t fbdiv = 0;
2160 uint32_t refdiv = 0;
2161
2162 fracin = io_read32(pllxcfgr3) & RCC_PLLxCFGR3_FRACIN_MASK;
2163 fbdiv = (io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >>
2164 RCC_PLLxCFGR2_FBDIV_SHIFT;
2165
2166 refdiv = io_read32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK;
2167
2168 assert(refdiv);
2169
2170 if (fracin) {
2171 unsigned long long numerator = 0;
2172 unsigned long long denominator = 0;
2173
2174 numerator = SHIFT_U64(fbdiv, 24) + fracin;
2175 numerator = prate * numerator;
2176 denominator = SHIFT_U64(refdiv, 24);
2177 fvco = (unsigned long)(numerator / denominator);
2178 } else {
2179 fvco = (unsigned long)(prate * fbdiv / refdiv);
2180 }
2181
2182 return fvco;
2183 }
2184
clk_stm32_pll_get_rate(struct clk * clk __unused,unsigned long prate)2185 static unsigned long clk_stm32_pll_get_rate(struct clk *clk __unused,
2186 unsigned long prate)
2187 {
2188 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2189 struct clk_stm32_pll_cfg *cfg = clk->priv;
2190 uintptr_t pllxcfgr1 = priv->base + cfg->pll_offset;
2191 uintptr_t pllxcfgr4 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR4;
2192 uintptr_t pllxcfgr6 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR6;
2193 uintptr_t pllxcfgr7 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR7;
2194 unsigned long dfout = 0;
2195 uint32_t postdiv1 = 0;
2196 uint32_t postdiv2 = 0;
2197
2198 postdiv1 = io_read32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK;
2199 postdiv2 = io_read32(pllxcfgr7) & RCC_PLLxCFGR7_POSTDIV2_MASK;
2200
2201 if ((io_read32(pllxcfgr4) & RCC_PLLxCFGR4_BYPASS) ||
2202 !postdiv1 || !postdiv2)
2203 dfout = prate;
2204 else
2205 dfout = clk_get_pll_fvco(cfg->pll_offset,
2206 prate) / (postdiv1 * postdiv2);
2207
2208 return dfout;
2209 }
2210
clk_stm32_pll_enable(struct clk * clk)2211 static TEE_Result clk_stm32_pll_enable(struct clk *clk)
2212 {
2213 struct clk_stm32_pll_cfg *cfg = clk->priv;
2214
2215 if (stm32_gate_rdy_enable(cfg->gate_id)) {
2216 EMSG("%s timeout", clk_get_name(clk));
2217 return TEE_ERROR_TIMEOUT;
2218 }
2219
2220 return TEE_SUCCESS;
2221 }
2222
clk_stm32_pll_disable(struct clk * clk)2223 static void clk_stm32_pll_disable(struct clk *clk)
2224 {
2225 struct clk_stm32_pll_cfg *cfg = clk->priv;
2226
2227 if (stm32_gate_rdy_disable(cfg->gate_id)) {
2228 EMSG("%s timeout", clk_get_name(clk));
2229 panic();
2230 }
2231 }
2232
2233 static const struct clk_ops clk_stm32_pll_ops = {
2234 .get_parent = clk_stm32_pll_get_parent,
2235 .get_rate = clk_stm32_pll_get_rate,
2236 .enable = clk_stm32_pll_enable,
2237 .disable = clk_stm32_pll_disable,
2238 };
2239
clk_stm32_pll3_enable(struct clk * clk)2240 static TEE_Result clk_stm32_pll3_enable(struct clk *clk)
2241 {
2242 struct clk_stm32_pll_cfg *cfg = clk->priv;
2243 struct clk_stm32_priv *priv = clk_stm32_get_priv();
2244 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(PLL3_ID);
2245 struct clk *parent = NULL;
2246 size_t pidx = 0;
2247
2248 /* ck_icn_p_gpu activate */
2249 stm32_gate_enable(GATE_GPU);
2250
2251 clk_stm32_pll_init(priv, PLL3_ID, pll_conf);
2252
2253 if (stm32_gate_rdy_enable(cfg->gate_id)) {
2254 EMSG("%s timeout", clk_get_name(clk));
2255 return TEE_ERROR_TIMEOUT;
2256 }
2257
2258 /* Update parent */
2259 pidx = clk_stm32_pll_get_parent(clk);
2260 parent = clk_get_parent_by_index(clk, pidx);
2261
2262 clk->parent = parent;
2263
2264 return TEE_SUCCESS;
2265 }
2266
clk_stm32_pll3_disable(struct clk * clk)2267 static void clk_stm32_pll3_disable(struct clk *clk)
2268 {
2269 clk_stm32_pll_disable(clk);
2270 stm32_gate_disable(GATE_GPU);
2271 }
2272
2273 static const struct clk_ops clk_stm32_pll3_ops = {
2274 .get_parent = clk_stm32_pll_get_parent,
2275 .get_rate = clk_stm32_pll_get_rate,
2276 .enable = clk_stm32_pll3_enable,
2277 .disable = clk_stm32_pll3_disable,
2278 };
2279
2280 struct clk_stm32_flexgen_cfg {
2281 int flex_id;
2282 };
2283
clk_stm32_flexgen_get_parent(struct clk * clk)2284 static size_t clk_stm32_flexgen_get_parent(struct clk *clk)
2285 {
2286 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2287 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2288 uint32_t address = 0;
2289
2290 address = rcc_base + RCC_XBAR0CFGR + (cfg->flex_id * 4);
2291
2292 return io_read32(address) & RCC_XBAR0CFGR_XBAR0SEL_MASK;
2293 }
2294
clk_stm32_flexgen_set_parent(struct clk * clk,size_t pidx)2295 static TEE_Result clk_stm32_flexgen_set_parent(struct clk *clk, size_t pidx)
2296 {
2297 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2298 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2299 uint16_t channel = cfg->flex_id * 4;
2300
2301 io_clrsetbits32(rcc_base + RCC_XBAR0CFGR + (channel),
2302 RCC_XBAR0CFGR_XBAR0SEL_MASK, pidx);
2303
2304 if (wait_xbar_sts(channel))
2305 return TEE_ERROR_GENERIC;
2306
2307 return TEE_SUCCESS;
2308 }
2309
clk_stm32_flexgen_get_rate(struct clk * clk,unsigned long prate)2310 static unsigned long clk_stm32_flexgen_get_rate(struct clk *clk,
2311 unsigned long prate)
2312 {
2313 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2314 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2315 uint32_t prediv = 0;
2316 uint32_t findiv = 0;
2317 uint8_t channel = cfg->flex_id;
2318 unsigned long freq = prate;
2319
2320 prediv = io_read32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel)) &
2321 RCC_PREDIV0CFGR_PREDIV0_MASK;
2322 findiv = io_read32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel)) &
2323 RCC_FINDIV0CFGR_FINDIV0_MASK;
2324
2325 if (!freq)
2326 return 0;
2327
2328 switch (prediv) {
2329 case 0x0:
2330 break;
2331
2332 case 0x1:
2333 freq /= 2;
2334 break;
2335
2336 case 0x3:
2337 freq /= 4;
2338 break;
2339
2340 case 0x3FF:
2341 freq /= 1024;
2342 break;
2343
2344 default:
2345 EMSG("Unsupported PREDIV value (%#"PRIx32")", prediv);
2346 panic();
2347 break;
2348 }
2349
2350 freq /= findiv + 1;
2351
2352 return freq;
2353 }
2354
clk_stm32_flexgen_get_round_rate(unsigned long rate,unsigned long prate,unsigned int * prediv,unsigned int * findiv)2355 static unsigned long clk_stm32_flexgen_get_round_rate(unsigned long rate,
2356 unsigned long prate,
2357 unsigned int *prediv,
2358 unsigned int *findiv)
2359 {
2360 unsigned int pre_val[] = { 0x0, 0x1, 0x3, 0x3FF };
2361 unsigned int pre_div[] = { 1, 2, 4, 1024 };
2362 long best_diff = LONG_MAX;
2363 unsigned int i = 0;
2364
2365 *prediv = 0;
2366 *findiv = 0;
2367
2368 for (i = 0; i < ARRAY_SIZE(pre_div); i++) {
2369 unsigned long freq = 0;
2370 unsigned long ratio = 0;
2371 long diff = 0L;
2372
2373 freq = UDIV_ROUND_NEAREST((uint64_t)prate, pre_div[i]);
2374 ratio = UDIV_ROUND_NEAREST((uint64_t)freq, rate);
2375
2376 if (!ratio)
2377 ratio = 1;
2378 else if (ratio > 64)
2379 ratio = 64;
2380
2381 freq = UDIV_ROUND_NEAREST((uint64_t)freq, ratio);
2382 if (freq < rate)
2383 diff = rate - freq;
2384 else
2385 diff = freq - rate;
2386
2387 if (diff < best_diff) {
2388 best_diff = diff;
2389 *prediv = pre_val[i];
2390 *findiv = ratio - 1;
2391
2392 if (!diff)
2393 break;
2394 }
2395 }
2396
2397 return (prate / (*prediv + 1)) / (*findiv + 1);
2398 }
2399
clk_stm32_flexgen_set_rate(struct clk * clk,unsigned long rate,unsigned long parent_rate)2400 static TEE_Result clk_stm32_flexgen_set_rate(struct clk *clk,
2401 unsigned long rate,
2402 unsigned long parent_rate)
2403 {
2404 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2405 uint8_t channel = cfg->flex_id;
2406 uintptr_t rcc_base = stm32_rcc_base();
2407 unsigned int prediv = 0;
2408 unsigned int findiv = 0;
2409
2410 clk_stm32_flexgen_get_round_rate(rate, parent_rate, &prediv, &findiv);
2411
2412 if (wait_predivsr(channel))
2413 panic();
2414
2415 io_clrsetbits32(rcc_base + RCC_PREDIV0CFGR + (0x4 * channel),
2416 RCC_PREDIV0CFGR_PREDIV0_MASK,
2417 prediv);
2418
2419 if (wait_predivsr(channel))
2420 panic();
2421
2422 if (wait_findivsr(channel))
2423 panic();
2424
2425 io_clrsetbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),
2426 RCC_FINDIV0CFGR_FINDIV0_MASK,
2427 findiv);
2428
2429 if (wait_findivsr(channel))
2430 panic();
2431
2432 return TEE_SUCCESS;
2433 }
2434
clk_stm32_flexgen_enable(struct clk * clk)2435 static TEE_Result clk_stm32_flexgen_enable(struct clk *clk)
2436 {
2437 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2438 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2439 TEE_Result ret = TEE_ERROR_GENERIC;
2440 uint8_t channel = cfg->flex_id;
2441
2442 /*
2443 * Configure flexgen of STGEN since it has been skipped during
2444 * flexgen configuration.
2445 */
2446 if (channel == FLEX_STGEN) {
2447 unsigned int clk_src = U(0);
2448 unsigned int pdiv = U(0);
2449 unsigned int fdiv = U(0);
2450
2451 ret = flexclkgen_search_config(channel, &clk_src, &pdiv, &fdiv);
2452 if (ret) {
2453 EMSG("Error %#"PRIx32" when getting STGEN flexgen conf",
2454 ret);
2455 return ret;
2456 }
2457
2458 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv);
2459
2460 /* Update parent */
2461 clk->parent = clk_get_parent_by_index(clk, clk_src);
2462 }
2463
2464 io_setbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),
2465 RCC_FINDIV0CFGR_FINDIV0EN);
2466
2467 return TEE_SUCCESS;
2468 }
2469
clk_stm32_flexgen_disable(struct clk * clk)2470 static void clk_stm32_flexgen_disable(struct clk *clk)
2471 {
2472 struct clk_stm32_flexgen_cfg *cfg = clk->priv;
2473 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2474 uint8_t channel = cfg->flex_id;
2475
2476 io_clrbits32(rcc_base + RCC_FINDIV0CFGR + (0x4 * channel),
2477 RCC_FINDIV0CFGR_FINDIV0EN);
2478 }
2479
2480 static const struct clk_ops clk_stm32_flexgen_ops = {
2481 .get_rate = clk_stm32_flexgen_get_rate,
2482 .set_rate = clk_stm32_flexgen_set_rate,
2483 .get_parent = clk_stm32_flexgen_get_parent,
2484 .set_parent = clk_stm32_flexgen_set_parent,
2485 .enable = clk_stm32_flexgen_enable,
2486 .disable = clk_stm32_flexgen_disable,
2487 };
2488
clk_cpu1_get_parent(struct clk * clk __unused)2489 static size_t clk_cpu1_get_parent(struct clk *clk __unused)
2490 {
2491 uint32_t reg = stm32mp_syscfg_read(CA35SS_SSC_CHGCLKREQ);
2492
2493 return (reg & CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_MASK) >>
2494 CA35SS_SSC_CHGCLKREQ_ARM_CHGCLKACK_SHIFT;
2495 }
2496
2497 static const struct clk_ops clk_stm32_cpu1_ops = {
2498 .get_parent = clk_cpu1_get_parent,
2499 };
2500
2501 #define APB_DIV_MASK GENMASK_32(2, 0)
2502 #define TIM_PRE_MASK BIT(0)
2503
ck_timer_get_rate_ops(struct clk * clk,unsigned long prate)2504 static unsigned long ck_timer_get_rate_ops(struct clk *clk, unsigned long prate)
2505 {
2506 struct clk_stm32_timer_cfg *cfg = clk->priv;
2507 uintptr_t rcc_base = clk_stm32_get_rcc_base();
2508 uint32_t prescaler = 0;
2509 uint32_t timpre = 0;
2510
2511 prescaler = io_read32(rcc_base + cfg->apbdiv) & APB_DIV_MASK;
2512
2513 timpre = io_read32(rcc_base + cfg->timpre) & TIM_PRE_MASK;
2514
2515 if (!prescaler)
2516 return prate;
2517
2518 return prate * (timpre + 1) * 2;
2519 };
2520
2521 static const struct clk_ops ck_timer_ops = {
2522 .get_rate = ck_timer_get_rate_ops,
2523 };
2524
2525 #define PLL_PARENTS { &ck_hsi, &ck_hse, &ck_msi }
2526 #define PLL_NUM_PATENTS 3
2527
2528 #define STM32_OSC(_name, _flags, _gate_id)\
2529 struct clk _name = {\
2530 .ops = &clk_stm32_osc_ops,\
2531 .priv = &(struct clk_stm32_gate_cfg){\
2532 .gate_id = (_gate_id),\
2533 },\
2534 .name = #_name,\
2535 .flags = (_flags),\
2536 .num_parents = 1,\
2537 .parents = { NULL },\
2538 }
2539
2540 #define STM32_OSC_MSI(_name, _flags, _gate_id)\
2541 struct clk _name = {\
2542 .ops = &clk_stm32_oscillator_msi_ops,\
2543 .priv = &(struct clk_stm32_gate_cfg){\
2544 .gate_id = (_gate_id),\
2545 },\
2546 .name = #_name,\
2547 .flags = (_flags),\
2548 .num_parents = 1,\
2549 .parents = { NULL },\
2550 }
2551
2552 #define STM32_HSE_DIV2(_name, _parent, _flags, _gate_id)\
2553 struct clk _name = {\
2554 .ops = &clk_hsediv2_ops,\
2555 .priv = &(struct clk_stm32_gate_cfg){\
2556 .gate_id = (_gate_id),\
2557 },\
2558 .name = #_name,\
2559 .flags = (_flags),\
2560 .num_parents = 1,\
2561 .parents = { (_parent) },\
2562 }
2563
2564 #define STM32_HSE_RTC(_name, _parent, _flags, _div_id)\
2565 struct clk _name = {\
2566 .ops = &clk_stm32_hse_div_ops,\
2567 .priv = &(struct clk_stm32_div_cfg){\
2568 .div_id = (_div_id),\
2569 },\
2570 .name = #_name,\
2571 .flags = (_flags),\
2572 .num_parents = 1,\
2573 .parents = { (_parent) },\
2574 }
2575
2576 #define STM32_PLL1(_name, _flags, _mux_id)\
2577 struct clk _name = {\
2578 .ops = &clk_stm32_pll1_ops,\
2579 .priv = &(struct clk_stm32_pll_cfg){\
2580 .mux_id = (_mux_id),\
2581 },\
2582 .name = #_name,\
2583 .flags = (_flags),\
2584 .num_parents = PLL_NUM_PATENTS,\
2585 .parents = PLL_PARENTS,\
2586 }
2587
2588 #define STM32_PLL2(_name, _flags, _reg, _gate_id, _mux_id)\
2589 struct clk _name = {\
2590 .ops = &clk_stm32_pll_ops,\
2591 .priv = &(struct clk_stm32_pll_cfg){\
2592 .pll_offset = (_reg),\
2593 .gate_id = (_gate_id),\
2594 .mux_id = (_mux_id),\
2595 },\
2596 .name = #_name,\
2597 .flags = (_flags),\
2598 .num_parents = PLL_NUM_PATENTS,\
2599 .parents = PLL_PARENTS,\
2600 }
2601
2602 #define STM32_PLL3(_name, _flags, _reg, _gate_id, _mux_id)\
2603 struct clk _name = {\
2604 .ops = &clk_stm32_pll3_ops,\
2605 .priv = &(struct clk_stm32_pll_cfg){\
2606 .pll_offset = (_reg),\
2607 .gate_id = (_gate_id),\
2608 .mux_id = (_mux_id),\
2609 },\
2610 .name = #_name,\
2611 .flags = (_flags),\
2612 .num_parents = PLL_NUM_PATENTS,\
2613 .parents = PLL_PARENTS,\
2614 }
2615
2616 #define STM32_PLLS(_name, _flags, _reg, _gate_id, _mux_id)\
2617 struct clk _name = {\
2618 .ops = &clk_stm32_pll_ops,\
2619 .priv = &(struct clk_stm32_pll_cfg){\
2620 .pll_offset = (_reg),\
2621 .gate_id = (_gate_id),\
2622 .mux_id = (_mux_id),\
2623 },\
2624 .name = #_name,\
2625 .flags = (_flags),\
2626 .num_parents = PLL_NUM_PATENTS,\
2627 .parents = PLL_PARENTS,\
2628 }
2629
2630 static STM32_FIXED_RATE(ck_off, RCC_0_MHZ);
2631
2632 static STM32_FIXED_RATE(ck_obser0, 0);
2633 static STM32_FIXED_RATE(ck_obser1, 0);
2634 static STM32_FIXED_RATE(spdifsymb, 0);
2635 static STM32_FIXED_RATE(txbyteclk, 27000000);
2636
2637 /* Oscillator clocks */
2638 static STM32_OSC(ck_hsi, 0, GATE_HSI);
2639 static STM32_OSC(ck_hse, 0, GATE_HSE);
2640 static STM32_OSC_MSI(ck_msi, 0, GATE_MSI);
2641 static STM32_OSC(ck_lsi, 0, GATE_LSI);
2642 static STM32_OSC(ck_lse, 0, GATE_LSE);
2643
2644 static STM32_HSE_DIV2(ck_hse_div2, &ck_hse, 0, GATE_HSEDIV2);
2645 static STM32_HSE_RTC(ck_hse_rtc, &ck_hse, 0, DIV_RTC);
2646
2647 static STM32_FIXED_FACTOR(i2sckin, NULL, 0, 1, 1);
2648
2649 static STM32_PLL1(ck_pll1, 0, MUX_MUXSEL5);
2650 static STM32_PLL2(ck_pll2, 0, RCC_PLL2CFGR1, GATE_PLL2, MUX_MUXSEL6);
2651 static STM32_PLL3(ck_pll3, 0, RCC_PLL3CFGR1, GATE_PLL3, MUX_MUXSEL7);
2652 static STM32_PLLS(ck_pll4, 0, RCC_PLL4CFGR1, GATE_PLL4, MUX_MUXSEL0);
2653 static STM32_PLLS(ck_pll5, 0, RCC_PLL5CFGR1, GATE_PLL5, MUX_MUXSEL1);
2654 static STM32_PLLS(ck_pll6, 0, RCC_PLL6CFGR1, GATE_PLL6, MUX_MUXSEL2);
2655 static STM32_PLLS(ck_pll7, 0, RCC_PLL7CFGR1, GATE_PLL7, MUX_MUXSEL3);
2656 static STM32_PLLS(ck_pll8, 0, RCC_PLL8CFGR1, GATE_PLL8, MUX_MUXSEL4);
2657
2658 #define STM32_FLEXGEN(_name, _flags, _flex_id)\
2659 struct clk _name = {\
2660 .ops = &clk_stm32_flexgen_ops,\
2661 .priv = &(struct clk_stm32_flexgen_cfg){\
2662 .flex_id = (_flex_id),\
2663 },\
2664 .name = #_name,\
2665 .flags = (_flags) | CLK_SET_RATE_UNGATE,\
2666 .num_parents = 15,\
2667 .parents = {\
2668 &ck_pll4, &ck_pll5, &ck_pll6, &ck_pll7, &ck_pll8,\
2669 &ck_hsi, &ck_hse, &ck_msi, &ck_hsi, &ck_hse, &ck_msi,\
2670 &spdifsymb, &i2sckin, &ck_lsi, &ck_lse\
2671 },\
2672 }
2673
2674 static STM32_FLEXGEN(ck_icn_hs_mcu, 0, 0);
2675 static STM32_FLEXGEN(ck_icn_sdmmc, 0, 1);
2676 static STM32_FLEXGEN(ck_icn_ddr, 0, 2);
2677 static STM32_FLEXGEN(ck_icn_display, 0, 3);
2678 static STM32_FLEXGEN(ck_icn_hsl, 0, 4);
2679 static STM32_FLEXGEN(ck_icn_nic, 0, 5);
2680 static STM32_FLEXGEN(ck_icn_vid, 0, 6);
2681
2682 static STM32_DIVIDER(ck_icn_ls_mcu, &ck_icn_hs_mcu, 0, DIV_LSMCU);
2683
2684 static STM32_FLEXGEN(ck_flexgen_07, 0, 7);
2685 static STM32_FLEXGEN(ck_flexgen_08, 0, 8);
2686 static STM32_FLEXGEN(ck_flexgen_09, 0, 9);
2687 static STM32_FLEXGEN(ck_flexgen_10, 0, 10);
2688 static STM32_FLEXGEN(ck_flexgen_11, 0, 11);
2689 static STM32_FLEXGEN(ck_flexgen_12, 0, 12);
2690 static STM32_FLEXGEN(ck_flexgen_13, 0, 13);
2691 static STM32_FLEXGEN(ck_flexgen_14, 0, 14);
2692 static STM32_FLEXGEN(ck_flexgen_15, 0, 15);
2693 static STM32_FLEXGEN(ck_flexgen_16, 0, 16);
2694 static STM32_FLEXGEN(ck_flexgen_17, 0, 17);
2695 static STM32_FLEXGEN(ck_flexgen_18, 0, 18);
2696 static STM32_FLEXGEN(ck_flexgen_19, 0, 19);
2697 static STM32_FLEXGEN(ck_flexgen_20, 0, 20);
2698 static STM32_FLEXGEN(ck_flexgen_21, 0, 21);
2699 static STM32_FLEXGEN(ck_flexgen_22, 0, 22);
2700 static STM32_FLEXGEN(ck_flexgen_23, 0, 23);
2701 static STM32_FLEXGEN(ck_flexgen_24, 0, 24);
2702 static STM32_FLEXGEN(ck_flexgen_25, 0, 25);
2703 static STM32_FLEXGEN(ck_flexgen_26, 0, 26);
2704 static STM32_FLEXGEN(ck_flexgen_27, 0, 27);
2705 static STM32_FLEXGEN(ck_flexgen_28, 0, 28);
2706 static STM32_FLEXGEN(ck_flexgen_29, 0, 29);
2707 static STM32_FLEXGEN(ck_flexgen_30, 0, 30);
2708 static STM32_FLEXGEN(ck_flexgen_31, 0, 31);
2709 static STM32_FLEXGEN(ck_flexgen_32, 0, 32);
2710 static STM32_FLEXGEN(ck_flexgen_33, 0, 33);
2711 static STM32_FLEXGEN(ck_flexgen_34, 0, 34);
2712 static STM32_FLEXGEN(ck_flexgen_35, 0, 35);
2713 static STM32_FLEXGEN(ck_flexgen_36, 0, 36);
2714 static STM32_FLEXGEN(ck_flexgen_37, 0, 37);
2715 static STM32_FLEXGEN(ck_flexgen_38, 0, 38);
2716 static STM32_FLEXGEN(ck_flexgen_39, 0, 39);
2717 static STM32_FLEXGEN(ck_flexgen_40, 0, 40);
2718 static STM32_FLEXGEN(ck_flexgen_41, 0, 41);
2719 static STM32_FLEXGEN(ck_flexgen_42, 0, 42);
2720 static STM32_FLEXGEN(ck_flexgen_43, 0, 43);
2721 static STM32_FLEXGEN(ck_flexgen_44, 0, 44);
2722 static STM32_FLEXGEN(ck_flexgen_45, 0, 45);
2723 static STM32_FLEXGEN(ck_flexgen_46, 0, 46);
2724 static STM32_FLEXGEN(ck_flexgen_47, 0, 47);
2725 static STM32_FLEXGEN(ck_flexgen_48, 0, 48);
2726 static STM32_FLEXGEN(ck_flexgen_49, 0, 49);
2727 static STM32_FLEXGEN(ck_flexgen_50, 0, 50);
2728 static STM32_FLEXGEN(ck_flexgen_51, 0, 51);
2729 static STM32_FLEXGEN(ck_flexgen_52, 0, 52);
2730 static STM32_FLEXGEN(ck_flexgen_53, 0, 53);
2731 static STM32_FLEXGEN(ck_flexgen_54, 0, 54);
2732 static STM32_FLEXGEN(ck_flexgen_55, 0, 55);
2733 static STM32_FLEXGEN(ck_flexgen_56, 0, 56);
2734 static STM32_FLEXGEN(ck_flexgen_57, 0, 57);
2735 static STM32_FLEXGEN(ck_flexgen_58, 0, 58);
2736 static STM32_FLEXGEN(ck_flexgen_59, 0, 59);
2737 static STM32_FLEXGEN(ck_flexgen_60, 0, 60);
2738 static STM32_FLEXGEN(ck_flexgen_61, 0, 61);
2739 static STM32_FLEXGEN(ck_flexgen_62, 0, 62);
2740 static STM32_FLEXGEN(ck_flexgen_63, 0, 63);
2741
2742 static struct clk ck_cpu1 = {
2743 .ops = &clk_stm32_cpu1_ops,
2744 .name = "ck_cpu1",
2745 .flags = CLK_SET_RATE_PARENT,
2746 .num_parents = 2,
2747 .parents = { &ck_pll1, &ck_flexgen_63 },
2748 };
2749
2750 static STM32_DIVIDER(ck_icn_apb1, &ck_icn_ls_mcu, 0, DIV_APB1);
2751 static STM32_DIVIDER(ck_icn_apb2, &ck_icn_ls_mcu, 0, DIV_APB2);
2752 static STM32_DIVIDER(ck_icn_apb3, &ck_icn_ls_mcu, 0, DIV_APB3);
2753 static STM32_DIVIDER(ck_icn_apb4, &ck_icn_ls_mcu, 0, DIV_APB4);
2754 static STM32_COMPOSITE(ck_icn_apbdbg, 1, { &ck_icn_ls_mcu }, 0,
2755 GATE_DBG, DIV_APBDBG, NO_MUX);
2756
2757 #define STM32_TIMER(_name, _parent, _flags, _apbdiv, _timpre)\
2758 struct clk _name = {\
2759 .ops = &ck_timer_ops,\
2760 .priv = &(struct clk_stm32_timer_cfg){\
2761 .apbdiv = (_apbdiv),\
2762 .timpre = (_timpre),\
2763 },\
2764 .name = #_name,\
2765 .flags = (_flags),\
2766 .num_parents = 1,\
2767 .parents = { _parent },\
2768 }
2769
2770 /* Kernel Timers */
2771 static STM32_TIMER(ck_timg1, &ck_icn_apb1, 0, RCC_APB1DIVR, RCC_TIMG1PRER);
2772 static STM32_TIMER(ck_timg2, &ck_icn_apb2, 0, RCC_APB2DIVR, RCC_TIMG2PRER);
2773
2774 /* Clocks under RCC RIF protection */
2775 static STM32_GATE(ck_sys_dbg, &ck_icn_apbdbg, 0, GATE_DBG);
2776 static STM32_GATE(ck_icn_p_stm, &ck_icn_apbdbg, 0, GATE_STM);
2777 static STM32_GATE(ck_icn_s_stm, &ck_icn_ls_mcu, 0, GATE_STM);
2778 static STM32_GATE(ck_ker_tsdbg, &ck_flexgen_43, 0, GATE_DBG);
2779 static STM32_GATE(ck_ker_tpiu, &ck_flexgen_44, 0, GATE_TRACE);
2780 static STM32_GATE(ck_icn_p_etr, &ck_icn_apbdbg, 0, GATE_ETR);
2781 static STM32_GATE(ck_icn_m_etr, &ck_flexgen_45, 0, GATE_ETR);
2782 static STM32_GATE(ck_sys_atb, &ck_flexgen_45, 0, GATE_DBG);
2783
2784 static STM32_GATE(ck_icn_s_sysram, &ck_icn_hs_mcu, 0, GATE_SYSRAM);
2785 static STM32_GATE(ck_icn_s_vderam, &ck_icn_hs_mcu, 0, GATE_VDERAM);
2786 static STM32_GATE(ck_icn_s_retram, &ck_icn_hs_mcu, 0, GATE_RETRAM);
2787 static STM32_GATE(ck_icn_s_bkpsram, &ck_icn_ls_mcu, 0, GATE_BKPSRAM);
2788 static STM32_GATE(ck_icn_s_sram1, &ck_icn_hs_mcu, 0, GATE_SRAM1);
2789 static STM32_GATE(ck_icn_s_sram2, &ck_icn_hs_mcu, 0, GATE_SRAM2);
2790 static STM32_GATE(ck_icn_s_lpsram1, &ck_icn_ls_mcu, 0, GATE_LPSRAM1);
2791 static STM32_GATE(ck_icn_s_lpsram2, &ck_icn_ls_mcu, 0, GATE_LPSRAM2);
2792 static STM32_GATE(ck_icn_s_lpsram3, &ck_icn_ls_mcu, 0, GATE_LPSRAM3);
2793 static STM32_GATE(ck_icn_p_hpdma1, &ck_icn_ls_mcu, 0, GATE_HPDMA1);
2794 static STM32_GATE(ck_icn_p_hpdma2, &ck_icn_ls_mcu, 0, GATE_HPDMA2);
2795 static STM32_GATE(ck_icn_p_hpdma3, &ck_icn_ls_mcu, 0, GATE_HPDMA3);
2796 static STM32_GATE(ck_icn_p_lpdma, &ck_icn_ls_mcu, 0, GATE_LPDMA);
2797 static STM32_GATE(ck_icn_p_ipcc1, &ck_icn_ls_mcu, 0, GATE_IPCC1);
2798 static STM32_GATE(ck_icn_p_ipcc2, &ck_icn_ls_mcu, 0, GATE_IPCC2);
2799 static STM32_GATE(ck_icn_p_hsem, &ck_icn_ls_mcu, 0, GATE_HSEM);
2800 static STM32_GATE(ck_icn_p_gpioa, &ck_icn_ls_mcu, 0, GATE_GPIOA);
2801 static STM32_GATE(ck_icn_p_gpiob, &ck_icn_ls_mcu, 0, GATE_GPIOB);
2802 static STM32_GATE(ck_icn_p_gpioc, &ck_icn_ls_mcu, 0, GATE_GPIOC);
2803 static STM32_GATE(ck_icn_p_gpiod, &ck_icn_ls_mcu, 0, GATE_GPIOD);
2804 static STM32_GATE(ck_icn_p_gpioe, &ck_icn_ls_mcu, 0, GATE_GPIOE);
2805 static STM32_GATE(ck_icn_p_gpiof, &ck_icn_ls_mcu, 0, GATE_GPIOF);
2806 static STM32_GATE(ck_icn_p_gpiog, &ck_icn_ls_mcu, 0, GATE_GPIOG);
2807 static STM32_GATE(ck_icn_p_gpioh, &ck_icn_ls_mcu, 0, GATE_GPIOH);
2808 static STM32_GATE(ck_icn_p_gpioi, &ck_icn_ls_mcu, 0, GATE_GPIOI);
2809 static STM32_GATE(ck_icn_p_gpioj, &ck_icn_ls_mcu, 0, GATE_GPIOJ);
2810 static STM32_GATE(ck_icn_p_gpiok, &ck_icn_ls_mcu, 0, GATE_GPIOK);
2811 static STM32_GATE(ck_icn_p_gpioz, &ck_icn_ls_mcu, 0, GATE_GPIOZ);
2812 static STM32_GATE(ck_icn_p_rtc, &ck_icn_ls_mcu, 0, GATE_RTC);
2813 static STM32_COMPOSITE(ck_rtc, 4,
2814 PARENT(&ck_off, &ck_lse, &ck_lsi, &ck_hse_rtc),
2815 0, GATE_RTCCK, NO_DIV, MUX_RTC);
2816 static STM32_GATE(ck_icn_p_bsec, &ck_icn_apb3, 0, GATE_BSEC);
2817 static STM32_GATE(ck_icn_p_ddrphyc, &ck_icn_ls_mcu, 0, GATE_DDRPHYCAPB);
2818 static STM32_GATE(ck_icn_p_risaf4, &ck_icn_ls_mcu, 0, GATE_DDRCP);
2819 static STM32_GATE(ck_icn_s_ddr, &ck_icn_ddr, 0, GATE_DDRCP);
2820 static STM32_GATE(ck_icn_p_ddrc, &ck_icn_apb4, 0, GATE_DDRCAPB);
2821 static STM32_GATE(ck_icn_p_ddrcfg, &ck_icn_apb4, 0, GATE_DDRCFG);
2822 static STM32_GATE(ck_icn_p_syscpu1, &ck_icn_ls_mcu, 0, GATE_SYSCPU1);
2823 static STM32_GATE(ck_icn_p_is2m, &ck_icn_apb3, 0, GATE_IS2M);
2824 static STM32_COMPOSITE(ck_mco1, 2, PARENT(&ck_flexgen_61, &ck_obser0), 0,
2825 GATE_MCO1, NO_DIV, MUX_MCO1);
2826 static STM32_COMPOSITE(ck_mco2, 2, PARENT(&ck_flexgen_62, &ck_obser1), 0,
2827 GATE_MCO2, NO_DIV, MUX_MCO2);
2828 static STM32_GATE(ck_icn_s_ospi1, &ck_icn_hs_mcu, 0, GATE_OSPI1);
2829 static STM32_GATE(ck_ker_ospi1, &ck_flexgen_48, 0, GATE_OSPI1);
2830 static STM32_GATE(ck_icn_s_ospi2, &ck_icn_hs_mcu, 0, GATE_OSPI2);
2831 static STM32_GATE(ck_ker_ospi2, &ck_flexgen_49, 0, GATE_OSPI2);
2832 static STM32_GATE(ck_icn_p_fmc, &ck_icn_ls_mcu, 0, GATE_FMC);
2833 static STM32_GATE(ck_ker_fmc, &ck_flexgen_50, 0, GATE_FMC);
2834
2835 /* Kernel Clocks */
2836 static STM32_GATE(ck_icn_p_cci, &ck_icn_ls_mcu, 0, GATE_CCI);
2837 static STM32_GATE(ck_icn_p_crc, &ck_icn_ls_mcu, 0, GATE_CRC);
2838 static STM32_GATE(ck_icn_p_ospiiom, &ck_icn_ls_mcu, 0, GATE_OSPIIOM);
2839 static STM32_GATE(ck_icn_p_hash, &ck_icn_ls_mcu, 0, GATE_HASH);
2840 static STM32_GATE(ck_icn_p_rng, &ck_icn_ls_mcu, 0, GATE_RNG);
2841 static STM32_GATE(ck_icn_p_cryp1, &ck_icn_ls_mcu, 0, GATE_CRYP1);
2842 static STM32_GATE(ck_icn_p_cryp2, &ck_icn_ls_mcu, 0, GATE_CRYP2);
2843 static STM32_GATE(ck_icn_p_saes, &ck_icn_ls_mcu, 0, GATE_SAES);
2844 static STM32_GATE(ck_icn_p_pka, &ck_icn_ls_mcu, 0, GATE_PKA);
2845 static STM32_GATE(ck_icn_p_adf1, &ck_icn_ls_mcu, 0, GATE_ADF1);
2846 static STM32_GATE(ck_icn_p_iwdg5, &ck_icn_ls_mcu, 0, GATE_IWDG5);
2847 static STM32_GATE(ck_icn_p_wwdg2, &ck_icn_ls_mcu, 0, GATE_WWDG2);
2848 static STM32_GATE(ck_icn_p_eth1, &ck_icn_ls_mcu, 0, GATE_ETH1);
2849 static STM32_GATE(ck_icn_p_ethsw, &ck_icn_ls_mcu, 0, GATE_ETHSWMAC);
2850 static STM32_GATE(ck_icn_p_eth2, &ck_icn_ls_mcu, 0, GATE_ETH2);
2851 static STM32_GATE(ck_icn_p_pcie, &ck_icn_ls_mcu, 0, GATE_PCIE);
2852 static STM32_GATE(ck_icn_p_adc12, &ck_icn_ls_mcu, 0, GATE_ADC12);
2853 static STM32_GATE(ck_icn_p_adc3, &ck_icn_ls_mcu, 0, GATE_ADC3);
2854 static STM32_GATE(ck_icn_p_mdf1, &ck_icn_ls_mcu, 0, GATE_MDF1);
2855 static STM32_GATE(ck_icn_p_spi8, &ck_icn_ls_mcu, 0, GATE_SPI8);
2856 static STM32_GATE(ck_icn_p_lpuart1, &ck_icn_ls_mcu, 0, GATE_LPUART1);
2857 static STM32_GATE(ck_icn_p_i2c8, &ck_icn_ls_mcu, 0, GATE_I2C8);
2858 static STM32_GATE(ck_icn_p_lptim3, &ck_icn_ls_mcu, 0, GATE_LPTIM3);
2859 static STM32_GATE(ck_icn_p_lptim4, &ck_icn_ls_mcu, 0, GATE_LPTIM4);
2860 static STM32_GATE(ck_icn_p_lptim5, &ck_icn_ls_mcu, 0, GATE_LPTIM5);
2861 static STM32_GATE(ck_icn_m_sdmmc1, &ck_icn_sdmmc, 0, GATE_SDMMC1);
2862 static STM32_GATE(ck_icn_m_sdmmc2, &ck_icn_sdmmc, 0, GATE_SDMMC2);
2863 static STM32_GATE(ck_icn_m_sdmmc3, &ck_icn_sdmmc, 0, GATE_SDMMC3);
2864 static STM32_GATE(ck_icn_m_usb2ohci, &ck_icn_hsl, 0, GATE_USB2);
2865 static STM32_GATE(ck_icn_m_usb2ehci, &ck_icn_hsl, 0, GATE_USB2);
2866 static STM32_GATE(ck_icn_m_usb3dr, &ck_icn_hsl, 0, GATE_USB3DR);
2867
2868 static STM32_GATE(ck_icn_p_tim2, &ck_icn_apb1, 0, GATE_TIM2);
2869 static STM32_GATE(ck_icn_p_tim3, &ck_icn_apb1, 0, GATE_TIM3);
2870 static STM32_GATE(ck_icn_p_tim4, &ck_icn_apb1, 0, GATE_TIM4);
2871 static STM32_GATE(ck_icn_p_tim5, &ck_icn_apb1, 0, GATE_TIM5);
2872 static STM32_GATE(ck_icn_p_tim6, &ck_icn_apb1, 0, GATE_TIM6);
2873 static STM32_GATE(ck_icn_p_tim7, &ck_icn_apb1, 0, GATE_TIM7);
2874 static STM32_GATE(ck_icn_p_tim10, &ck_icn_apb1, 0, GATE_TIM10);
2875 static STM32_GATE(ck_icn_p_tim11, &ck_icn_apb1, 0, GATE_TIM11);
2876 static STM32_GATE(ck_icn_p_tim12, &ck_icn_apb1, 0, GATE_TIM12);
2877 static STM32_GATE(ck_icn_p_tim13, &ck_icn_apb1, 0, GATE_TIM13);
2878 static STM32_GATE(ck_icn_p_tim14, &ck_icn_apb1, 0, GATE_TIM14);
2879 static STM32_GATE(ck_icn_p_lptim1, &ck_icn_apb1, 0, GATE_LPTIM1);
2880 static STM32_GATE(ck_icn_p_lptim2, &ck_icn_apb1, 0, GATE_LPTIM2);
2881 static STM32_GATE(ck_icn_p_spi2, &ck_icn_apb1, 0, GATE_SPI2);
2882 static STM32_GATE(ck_icn_p_spi3, &ck_icn_apb1, 0, GATE_SPI3);
2883 static STM32_GATE(ck_icn_p_spdifrx, &ck_icn_apb1, 0, GATE_SPDIFRX);
2884 static STM32_GATE(ck_icn_p_usart2, &ck_icn_apb1, 0, GATE_USART2);
2885 static STM32_GATE(ck_icn_p_usart3, &ck_icn_apb1, 0, GATE_USART3);
2886 static STM32_GATE(ck_icn_p_uart4, &ck_icn_apb1, 0, GATE_UART4);
2887 static STM32_GATE(ck_icn_p_uart5, &ck_icn_apb1, 0, GATE_UART5);
2888 static STM32_GATE(ck_icn_p_i2c1, &ck_icn_apb1, 0, GATE_I2C1);
2889 static STM32_GATE(ck_icn_p_i2c2, &ck_icn_apb1, 0, GATE_I2C2);
2890 static STM32_GATE(ck_icn_p_i2c3, &ck_icn_apb1, 0, GATE_I2C3);
2891 static STM32_GATE(ck_icn_p_i2c4, &ck_icn_apb1, 0, GATE_I2C4);
2892 static STM32_GATE(ck_icn_p_i2c5, &ck_icn_apb1, 0, GATE_I2C5);
2893 static STM32_GATE(ck_icn_p_i2c6, &ck_icn_apb1, 0, GATE_I2C6);
2894 static STM32_GATE(ck_icn_p_i2c7, &ck_icn_apb1, 0, GATE_I2C7);
2895 static STM32_GATE(ck_icn_p_i3c1, &ck_icn_apb1, 0, GATE_I3C1);
2896 static STM32_GATE(ck_icn_p_i3c2, &ck_icn_apb1, 0, GATE_I3C2);
2897 static STM32_GATE(ck_icn_p_i3c3, &ck_icn_apb1, 0, GATE_I3C3);
2898
2899 static STM32_GATE(ck_icn_p_i3c4, &ck_icn_ls_mcu, 0, GATE_I3C4);
2900
2901 static STM32_GATE(ck_icn_p_tim1, &ck_icn_apb2, 0, GATE_TIM1);
2902 static STM32_GATE(ck_icn_p_tim8, &ck_icn_apb2, 0, GATE_TIM8);
2903 static STM32_GATE(ck_icn_p_tim15, &ck_icn_apb2, 0, GATE_TIM15);
2904 static STM32_GATE(ck_icn_p_tim16, &ck_icn_apb2, 0, GATE_TIM16);
2905 static STM32_GATE(ck_icn_p_tim17, &ck_icn_apb2, 0, GATE_TIM17);
2906 static STM32_GATE(ck_icn_p_tim20, &ck_icn_apb2, 0, GATE_TIM20);
2907 static STM32_GATE(ck_icn_p_sai1, &ck_icn_apb2, 0, GATE_SAI1);
2908 static STM32_GATE(ck_icn_p_sai2, &ck_icn_apb2, 0, GATE_SAI2);
2909 static STM32_GATE(ck_icn_p_sai3, &ck_icn_apb2, 0, GATE_SAI3);
2910 static STM32_GATE(ck_icn_p_sai4, &ck_icn_apb2, 0, GATE_SAI4);
2911 static STM32_GATE(ck_icn_p_usart1, &ck_icn_apb2, 0, GATE_USART1);
2912 static STM32_GATE(ck_icn_p_usart6, &ck_icn_apb2, 0, GATE_USART6);
2913 static STM32_GATE(ck_icn_p_uart7, &ck_icn_apb2, 0, GATE_UART7);
2914 static STM32_GATE(ck_icn_p_uart8, &ck_icn_apb2, 0, GATE_UART8);
2915 static STM32_GATE(ck_icn_p_uart9, &ck_icn_apb2, 0, GATE_UART9);
2916 static STM32_GATE(ck_icn_p_fdcan, &ck_icn_apb2, 0, GATE_FDCAN);
2917 static STM32_GATE(ck_icn_p_spi1, &ck_icn_apb2, 0, GATE_SPI1);
2918 static STM32_GATE(ck_icn_p_spi4, &ck_icn_apb2, 0, GATE_SPI4);
2919 static STM32_GATE(ck_icn_p_spi5, &ck_icn_apb2, 0, GATE_SPI5);
2920 static STM32_GATE(ck_icn_p_spi6, &ck_icn_apb2, 0, GATE_SPI6);
2921 static STM32_GATE(ck_icn_p_spi7, &ck_icn_apb2, 0, GATE_SPI7);
2922 static STM32_GATE(ck_icn_p_iwdg1, &ck_icn_apb3, 0, GATE_IWDG1);
2923 static STM32_GATE(ck_icn_p_iwdg2, &ck_icn_apb3, 0, GATE_IWDG2);
2924 static STM32_GATE(ck_icn_p_iwdg3, &ck_icn_apb3, 0, GATE_IWDG3);
2925 static STM32_GATE(ck_icn_p_iwdg4, &ck_icn_apb3, 0, GATE_IWDG4);
2926 static STM32_GATE(ck_icn_p_wwdg1, &ck_icn_apb3, 0, GATE_WWDG1);
2927 static STM32_GATE(ck_icn_p_vref, &ck_icn_apb3, 0, GATE_VREF);
2928 static STM32_GATE(ck_icn_p_dts, &ck_icn_apb3, 0, GATE_DTS);
2929 static STM32_GATE(ck_icn_p_serc, &ck_icn_apb3, 0, GATE_SERC);
2930 static STM32_GATE(ck_icn_p_hdp, &ck_icn_apb3, 0, GATE_HDP);
2931 static STM32_GATE(ck_icn_p_dsi, &ck_icn_apb4, 0, GATE_DSI);
2932 static STM32_GATE(ck_icn_p_ltdc, &ck_icn_apb4, 0, GATE_LTDC);
2933 static STM32_GATE(ck_icn_p_csi, &ck_icn_apb4, 0, GATE_CSI);
2934 static STM32_GATE(ck_icn_p_dcmipp, &ck_icn_apb4, 0, GATE_DCMIPP);
2935 static STM32_GATE(ck_icn_p_lvds, &ck_icn_apb4, 0, GATE_LVDS);
2936 static STM32_GATE(ck_icn_p_gicv2m, &ck_icn_apb4, 0, GATE_GICV2M);
2937 static STM32_GATE(ck_icn_p_usbtc, &ck_icn_apb4, 0, GATE_USBTC);
2938 static STM32_GATE(ck_icn_p_usb3pciephy, &ck_icn_apb4, 0, GATE_USB3PCIEPHY);
2939 static STM32_GATE(ck_icn_p_stgen, &ck_icn_apb4, 0, GATE_STGEN);
2940 static STM32_GATE(ck_icn_p_vdec, &ck_icn_apb4, 0, GATE_VDEC);
2941 static STM32_GATE(ck_icn_p_venc, &ck_icn_apb4, 0, GATE_VENC);
2942
2943 static STM32_GATE(ck_ker_tim2, &ck_timg1, 0, GATE_TIM2);
2944 static STM32_GATE(ck_ker_tim3, &ck_timg1, 0, GATE_TIM3);
2945 static STM32_GATE(ck_ker_tim4, &ck_timg1, 0, GATE_TIM4);
2946 static STM32_GATE(ck_ker_tim5, &ck_timg1, 0, GATE_TIM5);
2947 static STM32_GATE(ck_ker_tim6, &ck_timg1, 0, GATE_TIM6);
2948 static STM32_GATE(ck_ker_tim7, &ck_timg1, 0, GATE_TIM7);
2949 static STM32_GATE(ck_ker_tim10, &ck_timg1, 0, GATE_TIM10);
2950 static STM32_GATE(ck_ker_tim11, &ck_timg1, 0, GATE_TIM11);
2951 static STM32_GATE(ck_ker_tim12, &ck_timg1, 0, GATE_TIM12);
2952 static STM32_GATE(ck_ker_tim13, &ck_timg1, 0, GATE_TIM13);
2953 static STM32_GATE(ck_ker_tim14, &ck_timg1, 0, GATE_TIM14);
2954 static STM32_GATE(ck_ker_tim1, &ck_timg2, 0, GATE_TIM1);
2955 static STM32_GATE(ck_ker_tim8, &ck_timg2, 0, GATE_TIM8);
2956 static STM32_GATE(ck_ker_tim15, &ck_timg2, 0, GATE_TIM15);
2957 static STM32_GATE(ck_ker_tim16, &ck_timg2, 0, GATE_TIM16);
2958 static STM32_GATE(ck_ker_tim17, &ck_timg2, 0, GATE_TIM17);
2959 static STM32_GATE(ck_ker_tim20, &ck_timg2, 0, GATE_TIM20);
2960 static STM32_GATE(ck_ker_lptim1, &ck_flexgen_07, 0, GATE_LPTIM1);
2961 static STM32_GATE(ck_ker_lptim2, &ck_flexgen_07, 0, GATE_LPTIM2);
2962 static STM32_GATE(ck_ker_usart2, &ck_flexgen_08, 0, GATE_USART2);
2963 static STM32_GATE(ck_ker_uart4, &ck_flexgen_08, 0, GATE_UART4);
2964 static STM32_GATE(ck_ker_usart3, &ck_flexgen_09, 0, GATE_USART3);
2965 static STM32_GATE(ck_ker_uart5, &ck_flexgen_09, 0, GATE_UART5);
2966 static STM32_GATE(ck_ker_spi2, &ck_flexgen_10, 0, GATE_SPI2);
2967 static STM32_GATE(ck_ker_spi3, &ck_flexgen_10, 0, GATE_SPI3);
2968 static STM32_GATE(ck_ker_spdifrx, &ck_flexgen_11, 0, GATE_SPDIFRX);
2969 static STM32_GATE(ck_ker_i2c1, &ck_flexgen_12, 0, GATE_I2C1);
2970 static STM32_GATE(ck_ker_i2c2, &ck_flexgen_12, 0, GATE_I2C2);
2971 static STM32_GATE(ck_ker_i3c1, &ck_flexgen_12, 0, GATE_I3C1);
2972 static STM32_GATE(ck_ker_i3c2, &ck_flexgen_12, 0, GATE_I3C2);
2973 static STM32_GATE(ck_ker_i2c3, &ck_flexgen_13, 0, GATE_I2C3);
2974 static STM32_GATE(ck_ker_i2c5, &ck_flexgen_13, 0, GATE_I2C5);
2975 static STM32_GATE(ck_ker_i3c3, &ck_flexgen_13, 0, GATE_I3C3);
2976 static STM32_GATE(ck_ker_i2c4, &ck_flexgen_14, 0, GATE_I2C4);
2977 static STM32_GATE(ck_ker_i2c6, &ck_flexgen_14, 0, GATE_I2C6);
2978 static STM32_GATE(ck_ker_i2c7, &ck_flexgen_15, 0, GATE_I2C7);
2979 static STM32_GATE(ck_ker_spi1, &ck_flexgen_16, 0, GATE_SPI1);
2980 static STM32_GATE(ck_ker_spi4, &ck_flexgen_17, 0, GATE_SPI4);
2981 static STM32_GATE(ck_ker_spi5, &ck_flexgen_17, 0, GATE_SPI5);
2982 static STM32_GATE(ck_ker_spi6, &ck_flexgen_18, 0, GATE_SPI6);
2983 static STM32_GATE(ck_ker_spi7, &ck_flexgen_18, 0, GATE_SPI7);
2984 static STM32_GATE(ck_ker_usart1, &ck_flexgen_19, 0, GATE_USART1);
2985 static STM32_GATE(ck_ker_usart6, &ck_flexgen_20, 0, GATE_USART6);
2986 static STM32_GATE(ck_ker_uart7, &ck_flexgen_21, 0, GATE_UART7);
2987 static STM32_GATE(ck_ker_uart8, &ck_flexgen_21, 0, GATE_UART8);
2988 static STM32_GATE(ck_ker_uart9, &ck_flexgen_22, 0, GATE_UART9);
2989 static STM32_GATE(ck_ker_mdf1, &ck_flexgen_23, 0, GATE_MDF1);
2990 static STM32_GATE(ck_ker_sai1, &ck_flexgen_23, 0, GATE_SAI1);
2991 static STM32_GATE(ck_ker_sai2, &ck_flexgen_24, 0, GATE_SAI2);
2992 static STM32_GATE(ck_ker_sai3, &ck_flexgen_25, 0, GATE_SAI3);
2993 static STM32_GATE(ck_ker_sai4, &ck_flexgen_25, 0, GATE_SAI4);
2994 static STM32_GATE(ck_ker_fdcan, &ck_flexgen_26, 0, GATE_FDCAN);
2995 static STM32_GATE(ck_ker_csi, &ck_flexgen_29, 0, GATE_CSI);
2996 static STM32_GATE(ck_ker_csitxesc, &ck_flexgen_30, 0, GATE_CSI);
2997 static STM32_GATE(ck_ker_csiphy, &ck_flexgen_31, 0, GATE_CSI);
2998 static STM32_GATE(ck_ker_stgen, &ck_flexgen_33, CLK_SET_RATE_PARENT,
2999 GATE_STGEN);
3000 static STM32_GATE(ck_ker_usbtc, &ck_flexgen_35, 0, GATE_USBTC);
3001 static STM32_GATE(ck_ker_i3c4, &ck_flexgen_36, 0, GATE_I3C4);
3002 static STM32_GATE(ck_ker_spi8, &ck_flexgen_37, 0, GATE_SPI8);
3003 static STM32_GATE(ck_ker_i2c8, &ck_flexgen_38, 0, GATE_I2C8);
3004 static STM32_GATE(ck_ker_lpuart1, &ck_flexgen_39, 0, GATE_LPUART1);
3005 static STM32_GATE(ck_ker_lptim3, &ck_flexgen_40, 0, GATE_LPTIM3);
3006 static STM32_GATE(ck_ker_lptim4, &ck_flexgen_41, 0, GATE_LPTIM4);
3007 static STM32_GATE(ck_ker_lptim5, &ck_flexgen_41, 0, GATE_LPTIM5);
3008 static STM32_GATE(ck_ker_adf1, &ck_flexgen_42, 0, GATE_ADF1);
3009 static STM32_GATE(ck_ker_sdmmc1, &ck_flexgen_51, 0, GATE_SDMMC1);
3010 static STM32_GATE(ck_ker_sdmmc2, &ck_flexgen_52, 0, GATE_SDMMC2);
3011 static STM32_GATE(ck_ker_sdmmc3, &ck_flexgen_53, 0, GATE_SDMMC3);
3012 static STM32_GATE(ck_ker_eth1, &ck_flexgen_54, 0, GATE_ETH1);
3013 static STM32_GATE(ck_ker_ethsw, &ck_flexgen_54, 0, GATE_ETHSW);
3014 static STM32_GATE(ck_ker_eth2, &ck_flexgen_55, 0, GATE_ETH2);
3015 static STM32_GATE(ck_ker_eth1ptp, &ck_flexgen_56, 0, GATE_ETH1);
3016 static STM32_GATE(ck_ker_eth2ptp, &ck_flexgen_56, 0, GATE_ETH2);
3017 static STM32_GATE(ck_ker_usb2phy2, &ck_flexgen_58, 0, GATE_USB3DR);
3018 static STM32_GATE(ck_icn_m_gpu, &ck_flexgen_59, 0, GATE_GPU);
3019 static STM32_GATE(ck_ker_gpu, &ck_pll3, 0, GATE_GPU);
3020 static STM32_GATE(ck_ker_ethswref, &ck_flexgen_60, 0, GATE_ETHSWREF);
3021
3022 static STM32_GATE(ck_ker_eth1stp, &ck_icn_ls_mcu, 0, GATE_ETH1STP);
3023 static STM32_GATE(ck_ker_eth2stp, &ck_icn_ls_mcu, 0, GATE_ETH2STP);
3024
3025 static STM32_GATE(ck_ker_ltdc, &ck_flexgen_27, CLK_SET_RATE_PARENT,
3026 GATE_LTDC);
3027
3028 static STM32_COMPOSITE(ck_ker_adc12, 2, PARENT(&ck_flexgen_46, &ck_icn_ls_mcu),
3029 0, GATE_ADC12, NO_DIV, MUX_ADC12);
3030
3031 static STM32_COMPOSITE(ck_ker_adc3, 3, PARENT(&ck_flexgen_47, &ck_icn_ls_mcu,
3032 &ck_flexgen_46),
3033 0, GATE_ADC3, NO_DIV, MUX_ADC3);
3034
3035 static STM32_COMPOSITE(ck_ker_usb2phy1, 2, PARENT(&ck_flexgen_57,
3036 &ck_hse_div2),
3037 0, GATE_USB2PHY1, NO_DIV, MUX_USB2PHY1);
3038
3039 static STM32_COMPOSITE(ck_ker_usb2phy2_en, 2, PARENT(&ck_flexgen_58,
3040 &ck_hse_div2),
3041 0, GATE_USB2PHY2, NO_DIV, MUX_USB2PHY2);
3042
3043 static STM32_COMPOSITE(ck_ker_usb3pciephy, 2, PARENT(&ck_flexgen_34,
3044 &ck_hse_div2),
3045 0, GATE_USB3PCIEPHY, NO_DIV, MUX_USB3PCIEPHY);
3046
3047 static STM32_COMPOSITE(clk_lanebyte, 2, PARENT(&txbyteclk, &ck_ker_ltdc),
3048 0, GATE_DSI, NO_DIV, MUX_DSIBLANE);
3049
3050 static STM32_COMPOSITE(ck_phy_dsi, 2, PARENT(&ck_flexgen_28, &ck_hse),
3051 0, GATE_DSI, NO_DIV, MUX_DSIPHY);
3052
3053 static STM32_COMPOSITE(ck_ker_lvdsphy, 2, PARENT(&ck_flexgen_32, &ck_hse),
3054 0, GATE_LVDS, NO_DIV, MUX_LVDSPHY);
3055
3056 static STM32_COMPOSITE(ck_ker_dts, 3, PARENT(&ck_hsi, &ck_hse, &ck_msi),
3057 0, GATE_DTS, NO_DIV, MUX_DTS);
3058
3059 enum {
3060 CK_OFF = STM32MP25_LAST_CLK,
3061 I2SCKIN,
3062 SPDIFSYMB,
3063 CK_HSE_RTC,
3064 TXBYTECLK,
3065 CK_OBSER0,
3066 CK_OBSER1,
3067 STM32MP25_ALL_CLK_NB
3068 };
3069
3070 static STM32_GATE(ck_ker_eth1mac, &ck_icn_ls_mcu, 0, GATE_ETH1MAC);
3071 static STM32_GATE(ck_ker_eth1tx, &ck_icn_ls_mcu, 0, GATE_ETH1TX);
3072 static STM32_GATE(ck_ker_eth1rx, &ck_icn_ls_mcu, 0, GATE_ETH1RX);
3073 static STM32_GATE(ck_ker_eth2mac, &ck_icn_ls_mcu, 0, GATE_ETH2MAC);
3074 static STM32_GATE(ck_ker_eth2tx, &ck_icn_ls_mcu, 0, GATE_ETH2TX);
3075 static STM32_GATE(ck_ker_eth2rx, &ck_icn_ls_mcu, 0, GATE_ETH2RX);
3076
3077 static struct clk *stm32mp25_clk_provided[STM32MP25_ALL_CLK_NB] = {
3078 [HSI_CK] = &ck_hsi,
3079 [HSE_CK] = &ck_hse,
3080 [MSI_CK] = &ck_msi,
3081 [LSI_CK] = &ck_lsi,
3082 [LSE_CK] = &ck_lse,
3083
3084 [HSE_DIV2_CK] = &ck_hse_div2,
3085
3086 [PLL1_CK] = &ck_pll1,
3087 [PLL2_CK] = &ck_pll2,
3088 [PLL3_CK] = &ck_pll3,
3089 [PLL4_CK] = &ck_pll4,
3090 [PLL5_CK] = &ck_pll5,
3091 [PLL6_CK] = &ck_pll6,
3092 [PLL7_CK] = &ck_pll7,
3093 [PLL8_CK] = &ck_pll8,
3094
3095 [CK_ICN_HS_MCU] = &ck_icn_hs_mcu,
3096 [CK_ICN_LS_MCU] = &ck_icn_ls_mcu,
3097
3098 [CK_ICN_SDMMC] = &ck_icn_sdmmc,
3099 [CK_ICN_DDR] = &ck_icn_ddr,
3100 [CK_ICN_DISPLAY] = &ck_icn_display,
3101 [CK_ICN_HSL] = &ck_icn_hsl,
3102 [CK_ICN_NIC] = &ck_icn_nic,
3103 [CK_ICN_VID] = &ck_icn_vid,
3104 [CK_FLEXGEN_07] = &ck_flexgen_07,
3105 [CK_FLEXGEN_08] = &ck_flexgen_08,
3106 [CK_FLEXGEN_09] = &ck_flexgen_09,
3107 [CK_FLEXGEN_10] = &ck_flexgen_10,
3108 [CK_FLEXGEN_11] = &ck_flexgen_11,
3109 [CK_FLEXGEN_12] = &ck_flexgen_12,
3110 [CK_FLEXGEN_13] = &ck_flexgen_13,
3111 [CK_FLEXGEN_14] = &ck_flexgen_14,
3112 [CK_FLEXGEN_15] = &ck_flexgen_15,
3113 [CK_FLEXGEN_16] = &ck_flexgen_16,
3114 [CK_FLEXGEN_17] = &ck_flexgen_17,
3115 [CK_FLEXGEN_18] = &ck_flexgen_18,
3116 [CK_FLEXGEN_19] = &ck_flexgen_19,
3117 [CK_FLEXGEN_20] = &ck_flexgen_20,
3118 [CK_FLEXGEN_21] = &ck_flexgen_21,
3119 [CK_FLEXGEN_22] = &ck_flexgen_22,
3120 [CK_FLEXGEN_23] = &ck_flexgen_23,
3121 [CK_FLEXGEN_24] = &ck_flexgen_24,
3122 [CK_FLEXGEN_25] = &ck_flexgen_25,
3123 [CK_FLEXGEN_26] = &ck_flexgen_26,
3124 [CK_FLEXGEN_27] = &ck_flexgen_27,
3125 [CK_FLEXGEN_28] = &ck_flexgen_28,
3126 [CK_FLEXGEN_29] = &ck_flexgen_29,
3127 [CK_FLEXGEN_30] = &ck_flexgen_30,
3128 [CK_FLEXGEN_31] = &ck_flexgen_31,
3129 [CK_FLEXGEN_32] = &ck_flexgen_32,
3130 [CK_FLEXGEN_33] = &ck_flexgen_33,
3131 [CK_FLEXGEN_34] = &ck_flexgen_34,
3132 [CK_FLEXGEN_35] = &ck_flexgen_35,
3133 [CK_FLEXGEN_36] = &ck_flexgen_36,
3134 [CK_FLEXGEN_37] = &ck_flexgen_37,
3135 [CK_FLEXGEN_38] = &ck_flexgen_38,
3136 [CK_FLEXGEN_39] = &ck_flexgen_39,
3137 [CK_FLEXGEN_40] = &ck_flexgen_40,
3138 [CK_FLEXGEN_41] = &ck_flexgen_41,
3139 [CK_FLEXGEN_42] = &ck_flexgen_42,
3140 [CK_FLEXGEN_43] = &ck_flexgen_43,
3141 [CK_FLEXGEN_44] = &ck_flexgen_44,
3142 [CK_FLEXGEN_45] = &ck_flexgen_45,
3143 [CK_FLEXGEN_46] = &ck_flexgen_46,
3144 [CK_FLEXGEN_47] = &ck_flexgen_47,
3145 [CK_FLEXGEN_48] = &ck_flexgen_48,
3146 [CK_FLEXGEN_49] = &ck_flexgen_49,
3147 [CK_FLEXGEN_50] = &ck_flexgen_50,
3148 [CK_FLEXGEN_51] = &ck_flexgen_51,
3149 [CK_FLEXGEN_52] = &ck_flexgen_52,
3150 [CK_FLEXGEN_53] = &ck_flexgen_53,
3151 [CK_FLEXGEN_54] = &ck_flexgen_54,
3152 [CK_FLEXGEN_55] = &ck_flexgen_55,
3153 [CK_FLEXGEN_56] = &ck_flexgen_56,
3154 [CK_FLEXGEN_57] = &ck_flexgen_57,
3155 [CK_FLEXGEN_58] = &ck_flexgen_58,
3156 [CK_FLEXGEN_59] = &ck_flexgen_59,
3157 [CK_FLEXGEN_60] = &ck_flexgen_60,
3158 [CK_FLEXGEN_61] = &ck_flexgen_61,
3159 [CK_FLEXGEN_62] = &ck_flexgen_62,
3160 [CK_FLEXGEN_63] = &ck_flexgen_63,
3161
3162 [CK_CPU1] = &ck_cpu1,
3163
3164 [CK_ICN_APB1] = &ck_icn_apb1,
3165 [CK_ICN_APB2] = &ck_icn_apb2,
3166 [CK_ICN_APB3] = &ck_icn_apb3,
3167 [CK_ICN_APB4] = &ck_icn_apb4,
3168 [CK_ICN_APBDBG] = &ck_icn_apbdbg,
3169
3170 [TIMG1_CK] = &ck_timg1,
3171 [TIMG2_CK] = &ck_timg2,
3172
3173 [CK_BUS_SYSRAM] = &ck_icn_s_sysram,
3174 [CK_BUS_VDERAM] = &ck_icn_s_vderam,
3175 [CK_BUS_RETRAM] = &ck_icn_s_retram,
3176 [CK_BUS_SRAM1] = &ck_icn_s_sram1,
3177 [CK_BUS_SRAM2] = &ck_icn_s_sram2,
3178 [CK_BUS_OSPI1] = &ck_icn_s_ospi1,
3179 [CK_BUS_OSPI2] = &ck_icn_s_ospi2,
3180 [CK_BUS_BKPSRAM] = &ck_icn_s_bkpsram,
3181 [CK_BUS_DDRPHYC] = &ck_icn_p_ddrphyc,
3182 [CK_BUS_SYSCPU1] = &ck_icn_p_syscpu1,
3183 [CK_BUS_HPDMA1] = &ck_icn_p_hpdma1,
3184 [CK_BUS_HPDMA2] = &ck_icn_p_hpdma2,
3185 [CK_BUS_HPDMA3] = &ck_icn_p_hpdma3,
3186 [CK_BUS_IPCC1] = &ck_icn_p_ipcc1,
3187 [CK_BUS_IPCC2] = &ck_icn_p_ipcc2,
3188 [CK_BUS_CCI] = &ck_icn_p_cci,
3189 [CK_BUS_CRC] = &ck_icn_p_crc,
3190 [CK_BUS_OSPIIOM] = &ck_icn_p_ospiiom,
3191 [CK_BUS_HASH] = &ck_icn_p_hash,
3192 [CK_BUS_RNG] = &ck_icn_p_rng,
3193 [CK_BUS_CRYP1] = &ck_icn_p_cryp1,
3194 [CK_BUS_CRYP2] = &ck_icn_p_cryp2,
3195 [CK_BUS_SAES] = &ck_icn_p_saes,
3196 [CK_BUS_PKA] = &ck_icn_p_pka,
3197 [CK_BUS_GPIOA] = &ck_icn_p_gpioa,
3198 [CK_BUS_GPIOB] = &ck_icn_p_gpiob,
3199 [CK_BUS_GPIOC] = &ck_icn_p_gpioc,
3200 [CK_BUS_GPIOD] = &ck_icn_p_gpiod,
3201 [CK_BUS_GPIOE] = &ck_icn_p_gpioe,
3202 [CK_BUS_GPIOF] = &ck_icn_p_gpiof,
3203 [CK_BUS_GPIOG] = &ck_icn_p_gpiog,
3204 [CK_BUS_GPIOH] = &ck_icn_p_gpioh,
3205 [CK_BUS_GPIOI] = &ck_icn_p_gpioi,
3206 [CK_BUS_GPIOJ] = &ck_icn_p_gpioj,
3207 [CK_BUS_GPIOK] = &ck_icn_p_gpiok,
3208 [CK_BUS_LPSRAM1] = &ck_icn_s_lpsram1,
3209 [CK_BUS_LPSRAM2] = &ck_icn_s_lpsram2,
3210 [CK_BUS_LPSRAM3] = &ck_icn_s_lpsram3,
3211 [CK_BUS_GPIOZ] = &ck_icn_p_gpioz,
3212 [CK_BUS_LPDMA] = &ck_icn_p_lpdma,
3213 [CK_BUS_ADF1] = &ck_icn_p_adf1,
3214 [CK_BUS_HSEM] = &ck_icn_p_hsem,
3215 [CK_BUS_RTC] = &ck_icn_p_rtc,
3216 [CK_BUS_IWDG5] = &ck_icn_p_iwdg5,
3217 [CK_BUS_WWDG2] = &ck_icn_p_wwdg2,
3218 [CK_BUS_STM] = &ck_icn_p_stm,
3219 [CK_KER_STM] = &ck_icn_s_stm,
3220 [CK_BUS_FMC] = &ck_icn_p_fmc,
3221 [CK_BUS_ETH1] = &ck_icn_p_eth1,
3222 [CK_BUS_ETHSW] = &ck_icn_p_ethsw,
3223 [CK_BUS_ETH2] = &ck_icn_p_eth2,
3224 [CK_BUS_PCIE] = &ck_icn_p_pcie,
3225 [CK_BUS_ADC12] = &ck_icn_p_adc12,
3226 [CK_BUS_ADC3] = &ck_icn_p_adc3,
3227 [CK_BUS_MDF1] = &ck_icn_p_mdf1,
3228 [CK_BUS_SPI8] = &ck_icn_p_spi8,
3229 [CK_BUS_LPUART1] = &ck_icn_p_lpuart1,
3230 [CK_BUS_I2C8] = &ck_icn_p_i2c8,
3231 [CK_BUS_LPTIM3] = &ck_icn_p_lptim3,
3232 [CK_BUS_LPTIM4] = &ck_icn_p_lptim4,
3233 [CK_BUS_LPTIM5] = &ck_icn_p_lptim5,
3234 [CK_BUS_RISAF4] = &ck_icn_p_risaf4,
3235 [CK_BUS_SDMMC1] = &ck_icn_m_sdmmc1,
3236 [CK_BUS_SDMMC2] = &ck_icn_m_sdmmc2,
3237 [CK_BUS_SDMMC3] = &ck_icn_m_sdmmc3,
3238 [CK_BUS_DDR] = &ck_icn_s_ddr,
3239 [CK_BUS_USB2OHCI] = &ck_icn_m_usb2ohci,
3240 [CK_BUS_USB2EHCI] = &ck_icn_m_usb2ehci,
3241 [CK_BUS_USB3DR] = &ck_icn_m_usb3dr,
3242 [CK_BUS_TIM2] = &ck_icn_p_tim2,
3243 [CK_BUS_TIM3] = &ck_icn_p_tim3,
3244 [CK_BUS_TIM4] = &ck_icn_p_tim4,
3245 [CK_BUS_TIM5] = &ck_icn_p_tim5,
3246 [CK_BUS_TIM6] = &ck_icn_p_tim6,
3247 [CK_BUS_TIM7] = &ck_icn_p_tim7,
3248 [CK_BUS_TIM10] = &ck_icn_p_tim10,
3249 [CK_BUS_TIM11] = &ck_icn_p_tim11,
3250 [CK_BUS_TIM12] = &ck_icn_p_tim12,
3251 [CK_BUS_TIM13] = &ck_icn_p_tim13,
3252 [CK_BUS_TIM14] = &ck_icn_p_tim14,
3253 [CK_BUS_LPTIM1] = &ck_icn_p_lptim1,
3254 [CK_BUS_LPTIM2] = &ck_icn_p_lptim2,
3255 [CK_BUS_SPI2] = &ck_icn_p_spi2,
3256 [CK_BUS_SPI3] = &ck_icn_p_spi3,
3257 [CK_BUS_SPDIFRX] = &ck_icn_p_spdifrx,
3258 [CK_BUS_USART2] = &ck_icn_p_usart2,
3259 [CK_BUS_USART3] = &ck_icn_p_usart3,
3260 [CK_BUS_UART4] = &ck_icn_p_uart4,
3261 [CK_BUS_UART5] = &ck_icn_p_uart5,
3262 [CK_BUS_I2C1] = &ck_icn_p_i2c1,
3263 [CK_BUS_I2C2] = &ck_icn_p_i2c2,
3264 [CK_BUS_I2C3] = &ck_icn_p_i2c3,
3265 [CK_BUS_I2C4] = &ck_icn_p_i2c4,
3266 [CK_BUS_I2C5] = &ck_icn_p_i2c5,
3267 [CK_BUS_I2C6] = &ck_icn_p_i2c6,
3268 [CK_BUS_I2C7] = &ck_icn_p_i2c7,
3269 [CK_BUS_I3C1] = &ck_icn_p_i3c1,
3270 [CK_BUS_I3C2] = &ck_icn_p_i3c2,
3271 [CK_BUS_I3C3] = &ck_icn_p_i3c3,
3272 [CK_BUS_I3C4] = &ck_icn_p_i3c4,
3273 [CK_BUS_TIM1] = &ck_icn_p_tim1,
3274 [CK_BUS_TIM8] = &ck_icn_p_tim8,
3275 [CK_BUS_TIM15] = &ck_icn_p_tim15,
3276 [CK_BUS_TIM16] = &ck_icn_p_tim16,
3277 [CK_BUS_TIM17] = &ck_icn_p_tim17,
3278 [CK_BUS_TIM20] = &ck_icn_p_tim20,
3279 [CK_BUS_SAI1] = &ck_icn_p_sai1,
3280 [CK_BUS_SAI2] = &ck_icn_p_sai2,
3281 [CK_BUS_SAI3] = &ck_icn_p_sai3,
3282 [CK_BUS_SAI4] = &ck_icn_p_sai4,
3283 [CK_BUS_USART1] = &ck_icn_p_usart1,
3284 [CK_BUS_USART6] = &ck_icn_p_usart6,
3285 [CK_BUS_UART7] = &ck_icn_p_uart7,
3286 [CK_BUS_UART8] = &ck_icn_p_uart8,
3287 [CK_BUS_UART9] = &ck_icn_p_uart9,
3288 [CK_BUS_FDCAN] = &ck_icn_p_fdcan,
3289 [CK_BUS_SPI1] = &ck_icn_p_spi1,
3290 [CK_BUS_SPI4] = &ck_icn_p_spi4,
3291 [CK_BUS_SPI5] = &ck_icn_p_spi5,
3292 [CK_BUS_SPI6] = &ck_icn_p_spi6,
3293 [CK_BUS_SPI7] = &ck_icn_p_spi7,
3294 [CK_BUS_BSEC] = &ck_icn_p_bsec,
3295 [CK_BUS_IWDG1] = &ck_icn_p_iwdg1,
3296 [CK_BUS_IWDG2] = &ck_icn_p_iwdg2,
3297 [CK_BUS_IWDG3] = &ck_icn_p_iwdg3,
3298 [CK_BUS_IWDG4] = &ck_icn_p_iwdg4,
3299 [CK_BUS_WWDG1] = &ck_icn_p_wwdg1,
3300 [CK_BUS_VREF] = &ck_icn_p_vref,
3301 [CK_BUS_SERC] = &ck_icn_p_serc,
3302 [CK_BUS_DTS] = &ck_icn_p_dts,
3303 [CK_BUS_HDP] = &ck_icn_p_hdp,
3304 [CK_BUS_IS2M] = &ck_icn_p_is2m,
3305 [CK_BUS_DSI] = &ck_icn_p_dsi,
3306 [CK_BUS_LTDC] = &ck_icn_p_ltdc,
3307 [CK_BUS_CSI] = &ck_icn_p_csi,
3308 [CK_BUS_DCMIPP] = &ck_icn_p_dcmipp,
3309 [CK_BUS_DDRC] = &ck_icn_p_ddrc,
3310 [CK_BUS_DDRCFG] = &ck_icn_p_ddrcfg,
3311 [CK_BUS_LVDS] = &ck_icn_p_lvds,
3312 [CK_BUS_GICV2M] = &ck_icn_p_gicv2m,
3313 [CK_BUS_USBTC] = &ck_icn_p_usbtc,
3314 [CK_BUS_USB3PCIEPHY] = &ck_icn_p_usb3pciephy,
3315 [CK_BUS_STGEN] = &ck_icn_p_stgen,
3316 [CK_BUS_VDEC] = &ck_icn_p_vdec,
3317 [CK_BUS_VENC] = &ck_icn_p_venc,
3318 [CK_SYSDBG] = &ck_sys_dbg,
3319 [CK_KER_TIM2] = &ck_ker_tim2,
3320 [CK_KER_TIM3] = &ck_ker_tim3,
3321 [CK_KER_TIM4] = &ck_ker_tim4,
3322 [CK_KER_TIM5] = &ck_ker_tim5,
3323 [CK_KER_TIM6] = &ck_ker_tim6,
3324 [CK_KER_TIM7] = &ck_ker_tim7,
3325 [CK_KER_TIM10] = &ck_ker_tim10,
3326 [CK_KER_TIM11] = &ck_ker_tim11,
3327 [CK_KER_TIM12] = &ck_ker_tim12,
3328 [CK_KER_TIM13] = &ck_ker_tim13,
3329 [CK_KER_TIM14] = &ck_ker_tim14,
3330 [CK_KER_TIM1] = &ck_ker_tim1,
3331 [CK_KER_TIM8] = &ck_ker_tim8,
3332 [CK_KER_TIM15] = &ck_ker_tim15,
3333 [CK_KER_TIM16] = &ck_ker_tim16,
3334 [CK_KER_TIM17] = &ck_ker_tim17,
3335 [CK_KER_TIM20] = &ck_ker_tim20,
3336 [CK_KER_LPTIM1] = &ck_ker_lptim1,
3337 [CK_KER_LPTIM2] = &ck_ker_lptim2,
3338 [CK_KER_USART2] = &ck_ker_usart2,
3339 [CK_KER_UART4] = &ck_ker_uart4,
3340 [CK_KER_USART3] = &ck_ker_usart3,
3341 [CK_KER_UART5] = &ck_ker_uart5,
3342 [CK_KER_SPI2] = &ck_ker_spi2,
3343 [CK_KER_SPI3] = &ck_ker_spi3,
3344 [CK_KER_SPDIFRX] = &ck_ker_spdifrx,
3345 [CK_KER_I2C1] = &ck_ker_i2c1,
3346 [CK_KER_I2C2] = &ck_ker_i2c2,
3347 [CK_KER_I3C1] = &ck_ker_i3c1,
3348 [CK_KER_I3C2] = &ck_ker_i3c2,
3349 [CK_KER_I2C3] = &ck_ker_i2c3,
3350 [CK_KER_I2C5] = &ck_ker_i2c5,
3351 [CK_KER_I3C3] = &ck_ker_i3c3,
3352 [CK_KER_I2C4] = &ck_ker_i2c4,
3353 [CK_KER_I2C6] = &ck_ker_i2c6,
3354 [CK_KER_I2C7] = &ck_ker_i2c7,
3355 [CK_KER_SPI1] = &ck_ker_spi1,
3356 [CK_KER_SPI4] = &ck_ker_spi4,
3357 [CK_KER_SPI5] = &ck_ker_spi5,
3358 [CK_KER_SPI6] = &ck_ker_spi6,
3359 [CK_KER_SPI7] = &ck_ker_spi7,
3360 [CK_KER_USART1] = &ck_ker_usart1,
3361 [CK_KER_USART6] = &ck_ker_usart6,
3362 [CK_KER_UART7] = &ck_ker_uart7,
3363 [CK_KER_UART8] = &ck_ker_uart8,
3364 [CK_KER_UART9] = &ck_ker_uart9,
3365 [CK_KER_MDF1] = &ck_ker_mdf1,
3366 [CK_KER_SAI1] = &ck_ker_sai1,
3367 [CK_KER_SAI2] = &ck_ker_sai2,
3368 [CK_KER_SAI3] = &ck_ker_sai3,
3369 [CK_KER_SAI4] = &ck_ker_sai4,
3370 [CK_KER_FDCAN] = &ck_ker_fdcan,
3371 [CK_KER_CSI] = &ck_ker_csi,
3372 [CK_KER_CSITXESC] = &ck_ker_csitxesc,
3373 [CK_KER_CSIPHY] = &ck_ker_csiphy,
3374 [CK_KER_STGEN] = &ck_ker_stgen,
3375 [CK_KER_USBTC] = &ck_ker_usbtc,
3376 [CK_KER_I3C4] = &ck_ker_i3c4,
3377 [CK_KER_SPI8] = &ck_ker_spi8,
3378 [CK_KER_I2C8] = &ck_ker_i2c8,
3379 [CK_KER_LPUART1] = &ck_ker_lpuart1,
3380 [CK_KER_LPTIM3] = &ck_ker_lptim3,
3381 [CK_KER_LPTIM4] = &ck_ker_lptim4,
3382 [CK_KER_LPTIM5] = &ck_ker_lptim5,
3383 [CK_KER_ADF1] = &ck_ker_adf1,
3384 [CK_KER_TSDBG] = &ck_ker_tsdbg,
3385 [CK_KER_TPIU] = &ck_ker_tpiu,
3386 [CK_BUS_ETR] = &ck_icn_p_etr,
3387 [CK_KER_ETR] = &ck_icn_m_etr,
3388 [CK_BUS_SYSATB] = &ck_sys_atb,
3389 [CK_KER_OSPI1] = &ck_ker_ospi1,
3390 [CK_KER_OSPI2] = &ck_ker_ospi2,
3391 [CK_KER_FMC] = &ck_ker_fmc,
3392 [CK_KER_SDMMC1] = &ck_ker_sdmmc1,
3393 [CK_KER_SDMMC2] = &ck_ker_sdmmc2,
3394 [CK_KER_SDMMC3] = &ck_ker_sdmmc3,
3395 [CK_KER_ETH1] = &ck_ker_eth1,
3396 [CK_ETH1_STP] = &ck_ker_eth1stp,
3397 [CK_KER_ETHSW] = &ck_ker_ethsw,
3398 [CK_KER_ETH2] = &ck_ker_eth2,
3399 [CK_ETH2_STP] = &ck_ker_eth2stp,
3400 [CK_KER_ETH1PTP] = &ck_ker_eth1ptp,
3401 [CK_KER_ETH2PTP] = &ck_ker_eth2ptp,
3402 [CK_BUS_GPU] = &ck_icn_m_gpu,
3403 [CK_KER_GPU] = &ck_ker_gpu,
3404 [CK_KER_ETHSWREF] = &ck_ker_ethswref,
3405
3406 [CK_MCO1] = &ck_mco1,
3407 [CK_MCO2] = &ck_mco2,
3408 [CK_KER_ADC12] = &ck_ker_adc12,
3409 [CK_KER_ADC3] = &ck_ker_adc3,
3410 [CK_KER_USB2PHY1] = &ck_ker_usb2phy1,
3411 [CK_KER_USB2PHY2] = &ck_ker_usb2phy2,
3412 [CK_KER_USB2PHY2EN] = &ck_ker_usb2phy2_en,
3413 [CK_KER_USB3PCIEPHY] = &ck_ker_usb3pciephy,
3414 [CK_KER_LTDC] = &ck_ker_ltdc,
3415 [CK_KER_DSIBLANE] = &clk_lanebyte,
3416 [CK_KER_DSIPHY] = &ck_phy_dsi,
3417 [CK_KER_LVDSPHY] = &ck_ker_lvdsphy,
3418 [CK_KER_DTS] = &ck_ker_dts,
3419 [RTC_CK] = &ck_rtc,
3420
3421 [CK_ETH1_MAC] = &ck_ker_eth1mac,
3422 [CK_ETH1_TX] = &ck_ker_eth1tx,
3423 [CK_ETH1_RX] = &ck_ker_eth1rx,
3424 [CK_ETH2_MAC] = &ck_ker_eth2mac,
3425 [CK_ETH2_TX] = &ck_ker_eth2tx,
3426 [CK_ETH2_RX] = &ck_ker_eth2rx,
3427
3428 [CK_HSE_RTC] = &ck_hse_rtc,
3429 [CK_OBSER0] = &ck_obser0,
3430 [CK_OBSER1] = &ck_obser1,
3431 [CK_OFF] = &ck_off,
3432 [I2SCKIN] = &i2sckin,
3433 [SPDIFSYMB] = &spdifsymb,
3434 [TXBYTECLK] = &txbyteclk,
3435 };
3436
clk_stm32_clock_is_critical(struct clk * clk)3437 static bool clk_stm32_clock_is_critical(struct clk *clk)
3438 {
3439 struct clk *clk_criticals[] = {
3440 &ck_hsi,
3441 &ck_hse,
3442 &ck_msi,
3443 &ck_lsi,
3444 &ck_lse,
3445 &ck_cpu1,
3446 &ck_icn_p_syscpu1,
3447 &ck_icn_s_ddr,
3448 &ck_icn_p_ddrc,
3449 &ck_icn_p_ddrcfg,
3450 &ck_icn_p_ddrphyc,
3451 &ck_icn_s_sysram,
3452 &ck_icn_s_bkpsram,
3453 &ck_ker_fmc,
3454 &ck_ker_ospi1,
3455 &ck_ker_ospi2,
3456 &ck_icn_s_vderam,
3457 &ck_icn_s_lpsram1,
3458 &ck_icn_s_lpsram2,
3459 &ck_icn_s_lpsram3,
3460 &ck_icn_p_hpdma1,
3461 &ck_icn_p_hpdma2,
3462 &ck_icn_p_hpdma3,
3463 &ck_icn_p_gpioa,
3464 &ck_icn_p_gpiob,
3465 &ck_icn_p_gpioc,
3466 &ck_icn_p_gpiod,
3467 &ck_icn_p_gpioe,
3468 &ck_icn_p_gpiof,
3469 &ck_icn_p_gpiog,
3470 &ck_icn_p_gpioh,
3471 &ck_icn_p_gpioi,
3472 &ck_icn_p_gpioj,
3473 &ck_icn_p_gpiok,
3474 &ck_icn_p_gpioz,
3475 &ck_icn_p_ipcc1,
3476 &ck_icn_p_ipcc2,
3477 &ck_icn_p_gicv2m,
3478 &ck_icn_p_rtc
3479 };
3480 size_t i = 0;
3481
3482 for (i = 0; i < ARRAY_SIZE(clk_criticals); i++)
3483 if (clk == clk_criticals[i])
3484 return true;
3485 return false;
3486 }
3487
clk_stm32_init_oscillators(const void * fdt,int node)3488 static void clk_stm32_init_oscillators(const void *fdt, int node)
3489 {
3490 size_t i = 0;
3491 static const char * const name[] = {
3492 "clk-hse", "clk-hsi", "clk-lse",
3493 "clk-lsi", "clk-msi", "clk-i2sin"
3494 };
3495 struct clk *clks[ARRAY_SIZE(name)] = {
3496 &ck_hse, &ck_hsi, &ck_lse,
3497 &ck_lsi, &ck_msi, &i2sckin
3498 };
3499
3500 for (i = 0; i < ARRAY_SIZE(clks); i++) {
3501 struct clk *clk = NULL;
3502
3503 if (clk_dt_get_by_name(fdt, node, name[i], &clk))
3504 panic();
3505
3506 clks[i]->parents[0] = clk;
3507 }
3508 }
3509
clk_stm32_apply_rcc_config(struct stm32_clk_platdata * pdata)3510 static TEE_Result clk_stm32_apply_rcc_config(struct stm32_clk_platdata *pdata)
3511 {
3512 if (pdata->safe_rst)
3513 stm32mp25_syscfg_set_safe_reset(true);
3514
3515 return TEE_SUCCESS;
3516 }
3517
3518 static struct stm32_pll_dt_cfg mp25_pll[PLL_NB];
3519 static struct stm32_clk_opp_dt_cfg mp25_clk_opp;
3520 static struct stm32_osci_dt_cfg mp25_osci[NB_OSCILLATOR];
3521
3522 #define DT_FLEXGEN_CLK_MAX 64
3523 static uint32_t mp25_flexgen[DT_FLEXGEN_CLK_MAX];
3524
3525 #define DT_BUS_CLK_MAX 6
3526 static uint32_t mp25_busclk[DT_BUS_CLK_MAX];
3527
3528 #define DT_KERNEL_CLK_MAX 20
3529 static uint32_t mp25_kernelclk[DT_KERNEL_CLK_MAX];
3530
3531 static struct stm32_clk_platdata stm32mp25_clock_pdata = {
3532 .osci = mp25_osci,
3533 .nosci = NB_OSCILLATOR,
3534 .pll = mp25_pll,
3535 .npll = PLL_NB,
3536 .opp = &mp25_clk_opp,
3537 .busclk = mp25_busclk,
3538 .nbusclk = DT_BUS_CLK_MAX,
3539 .kernelclk = mp25_kernelclk,
3540 .nkernelclk = DT_KERNEL_CLK_MAX,
3541 .flexgen = mp25_flexgen,
3542 .nflexgen = DT_FLEXGEN_CLK_MAX,
3543 };
3544
3545 static struct clk_stm32_priv stm32mp25_clock_data = {
3546 .muxes = parent_mp25,
3547 .nb_muxes = ARRAY_SIZE(parent_mp25),
3548 .gates = gates_mp25,
3549 .nb_gates = ARRAY_SIZE(gates_mp25),
3550 .div = dividers_mp25,
3551 .nb_div = ARRAY_SIZE(dividers_mp25),
3552 .pdata = &stm32mp25_clock_pdata,
3553 .nb_clk_refs = STM32MP25_ALL_CLK_NB,
3554 .clk_refs = stm32mp25_clk_provided,
3555 .is_critical = clk_stm32_clock_is_critical,
3556 };
3557
handle_available_semaphores(void)3558 static TEE_Result handle_available_semaphores(void)
3559 {
3560 struct stm32_clk_platdata *pdata = &stm32mp25_clock_pdata;
3561 TEE_Result res = TEE_ERROR_GENERIC;
3562 unsigned int index = 0;
3563 uint32_t cidcfgr = 0;
3564 unsigned int i = 0;
3565
3566 for (i = 0; i < RCC_NB_RIF_RES; i++) {
3567 vaddr_t reg_offset = pdata->rcc_base + RCC_SEMCR(i);
3568
3569 index = i / 32;
3570
3571 if (!(BIT(i % 32) & pdata->conf_data.access_mask[index]))
3572 continue;
3573
3574 cidcfgr = io_read32(pdata->rcc_base + RCC_CIDCFGR(i));
3575
3576 if (!stm32_rif_semaphore_enabled_and_ok(cidcfgr, RIF_CID1))
3577 continue;
3578
3579 if (!(io_read32(pdata->rcc_base + RCC_SECCFGR(index)) &
3580 BIT(i % 32))) {
3581 res = stm32_rif_release_semaphore(reg_offset,
3582 MAX_CID_SUPPORTED);
3583 if (res) {
3584 EMSG("Cannot release semaphore for res %u", i);
3585 return res;
3586 }
3587 } else {
3588 res = stm32_rif_acquire_semaphore(reg_offset,
3589 MAX_CID_SUPPORTED);
3590 if (res) {
3591 EMSG("Cannot acquire semaphore for res %u", i);
3592 return res;
3593 }
3594 }
3595 }
3596
3597 return TEE_SUCCESS;
3598 }
3599
apply_rcc_rif_config(bool is_tdcid)3600 static TEE_Result apply_rcc_rif_config(bool is_tdcid)
3601 {
3602 TEE_Result res = TEE_ERROR_ACCESS_DENIED;
3603 struct stm32_clk_platdata *pdata = &stm32mp25_clock_pdata;
3604 unsigned int i = 0;
3605 unsigned int index = 0;
3606
3607 if (is_tdcid) {
3608 /*
3609 * When TDCID, OP-TEE should be the one to set the CID
3610 * filtering configuration. Clearing previous configuration
3611 * prevents undesired events during the only legitimate
3612 * configuration.
3613 */
3614 for (i = 0; i < RCC_NB_RIF_RES; i++) {
3615 if (BIT(i % 32) & pdata->conf_data.access_mask[i / 32])
3616 io_clrbits32(pdata->rcc_base + RCC_CIDCFGR(i),
3617 RCC_CIDCFGR_CONF_MASK);
3618 }
3619 } else {
3620 res = handle_available_semaphores();
3621 if (res)
3622 panic();
3623 }
3624
3625 /* Security and privilege RIF configuration */
3626 for (index = 0; index < RCC_NB_CONFS; index++) {
3627 io_clrsetbits32(pdata->rcc_base + RCC_PRIVCFGR(index),
3628 pdata->conf_data.access_mask[index],
3629 pdata->conf_data.priv_conf[index]);
3630 io_clrsetbits32(pdata->rcc_base + RCC_SECCFGR(index),
3631 pdata->conf_data.access_mask[index],
3632 pdata->conf_data.sec_conf[index]);
3633 }
3634
3635 if (!is_tdcid)
3636 goto end;
3637
3638 for (i = 0; i < RCC_NB_RIF_RES; i++) {
3639 if (BIT(i % 32) & pdata->conf_data.access_mask[i / 32])
3640 io_clrsetbits32(pdata->rcc_base + RCC_CIDCFGR(i),
3641 RCC_CIDCFGR_CONF_MASK,
3642 pdata->conf_data.cid_confs[i]);
3643 }
3644
3645 for (index = 0; index < RCC_NB_CONFS; index++)
3646 io_setbits32(pdata->rcc_base + RCC_RCFGLOCKR(index),
3647 pdata->conf_data.lock_conf[index]);
3648
3649 res = handle_available_semaphores();
3650 if (res)
3651 panic();
3652 end:
3653 if (IS_ENABLED(CFG_TEE_CORE_DEBUG)) {
3654 for (index = 0; index < RCC_NB_CONFS; index++) {
3655 /* Check that RIF config are applied, panic otherwise */
3656 if ((io_read32(pdata->rcc_base + RCC_PRIVCFGR(index)) &
3657 pdata->conf_data.access_mask[index]) !=
3658 pdata->conf_data.priv_conf[index])
3659 panic("rcc resource prv conf is incorrect");
3660
3661 if ((io_read32(pdata->rcc_base + RCC_SECCFGR(index)) &
3662 pdata->conf_data.access_mask[index]) !=
3663 pdata->conf_data.sec_conf[index])
3664 panic("rcc resource sec conf is incorrect");
3665 }
3666 }
3667
3668 return TEE_SUCCESS;
3669 }
3670
stm32_rcc_rif_pm_suspend(void)3671 static TEE_Result stm32_rcc_rif_pm_suspend(void)
3672 {
3673 struct stm32_clk_platdata *pdata = &stm32mp25_clock_pdata;
3674 unsigned int i = 0;
3675
3676 if (!pdata->nb_res)
3677 return TEE_SUCCESS;
3678
3679 for (i = 0; i < RCC_NB_RIF_RES; i++)
3680 pdata->conf_data.cid_confs[i] = io_read32(pdata->rcc_base +
3681 RCC_CIDCFGR(i));
3682
3683 for (i = 0; i < RCC_NB_CONFS; i++) {
3684 pdata->conf_data.priv_conf[i] = io_read32(pdata->rcc_base +
3685 RCC_PRIVCFGR(i));
3686 pdata->conf_data.sec_conf[i] = io_read32(pdata->rcc_base +
3687 RCC_SECCFGR(i));
3688 pdata->conf_data.lock_conf[i] = io_read32(pdata->rcc_base +
3689 RCC_RCFGLOCKR(i));
3690 pdata->conf_data.access_mask[i] = GENMASK_32(31, 0);
3691 }
3692
3693 return TEE_SUCCESS;
3694 }
3695
stm32_rcc_rif_pm(enum pm_op op,unsigned int pm_hint,const struct pm_callback_handle * h __unused)3696 static TEE_Result stm32_rcc_rif_pm(enum pm_op op, unsigned int pm_hint,
3697 const struct pm_callback_handle *h __unused)
3698 {
3699 TEE_Result res = TEE_ERROR_GENERIC;
3700 bool is_tdcid = false;
3701
3702 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT))
3703 return TEE_SUCCESS;
3704
3705 res = stm32_rifsc_check_tdcid(&is_tdcid);
3706 if (res)
3707 return res;
3708
3709 if (op == PM_OP_RESUME) {
3710 if (is_tdcid)
3711 res = apply_rcc_rif_config(true);
3712 else
3713 res = handle_available_semaphores();
3714 } else {
3715 if (!is_tdcid)
3716 return TEE_SUCCESS;
3717
3718 res = stm32_rcc_rif_pm_suspend();
3719 }
3720
3721 return res;
3722 }
3723
rcc_rif_config(void)3724 static TEE_Result rcc_rif_config(void)
3725 {
3726 TEE_Result res = TEE_ERROR_ACCESS_DENIED;
3727 bool is_tdcid = false;
3728
3729 /* Not expected to fail at this stage */
3730 res = stm32_rifsc_check_tdcid(&is_tdcid);
3731 if (res)
3732 panic();
3733
3734 res = apply_rcc_rif_config(is_tdcid);
3735 if (res)
3736 panic();
3737
3738 register_pm_core_service_cb(stm32_rcc_rif_pm, NULL, "stm32-rcc-rif");
3739
3740 return TEE_SUCCESS;
3741 }
3742
3743 driver_init_late(rcc_rif_config);
3744
stm32mp25_clk_probe(const void * fdt,int node,const void * compat_data __unused)3745 static TEE_Result stm32mp25_clk_probe(const void *fdt, int node,
3746 const void *compat_data __unused)
3747 {
3748 TEE_Result res = TEE_ERROR_GENERIC;
3749 int fdt_rc = 0;
3750 int rc = 0;
3751 struct clk_stm32_priv *priv = &stm32mp25_clock_data;
3752 struct stm32_clk_platdata *pdata = &stm32mp25_clock_pdata;
3753
3754 fdt_rc = stm32_clk_parse_fdt(fdt, node, pdata);
3755 if (fdt_rc) {
3756 EMSG("Failed to parse clock node %s: %d",
3757 fdt_get_name(fdt, node, NULL), fdt_rc);
3758 return TEE_ERROR_GENERIC;
3759 }
3760
3761 rc = clk_stm32_init(priv, stm32_rcc_base());
3762 if (rc)
3763 return TEE_ERROR_GENERIC;
3764
3765 stm32mp2_init_clock_tree(priv, pdata);
3766
3767 clk_stm32_init_oscillators(fdt, node);
3768
3769 res = clk_stm32_apply_rcc_config(pdata);
3770 if (res)
3771 panic("Error when applying RCC config");
3772
3773 stm32mp_clk_provider_probe_final(fdt, node, priv);
3774
3775 if (IS_ENABLED(CFG_STM32_CLK_DEBUG))
3776 clk_print_tree();
3777
3778 return TEE_SUCCESS;
3779 }
3780
3781 CLK_DT_DECLARE(stm32mp25_clk, "st,stm32mp25-rcc", stm32mp25_clk_probe);
3782