| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdv3/ |
| H A D | rdv3_sfcp.c | 56 for (uint8_t i = 1; i < ARRAY_SIZE(receiver_devices); i++) { in sfcp_platform_get_receive_link_id() local
57 if ((receiver_devices[i].type == device.type) && in sfcp_platform_get_receive_link_id()
58 (receiver_devices[i].device == device.device)) { in sfcp_platform_get_receive_link_id()
59 return i; in sfcp_platform_get_receive_link_id()
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| /rk3399_ARM-atf/lib/debugfs/ |
| H A D | dev.c | 38 int i; in create_new_channel() local
40 for (i = 0; i < NR_CHANS; i++) { in create_new_channel()
41 if (fdset[i].index == NODEV) { in create_new_channel()
42 channel = &fdset[i]; in create_new_channel()
261 int i, n; in path_to_channel() local
282 for (i = 1; (elem[i] >= '0') && (elem[i] <= '9'); i++) { in path_to_channel()
283 n += elem[i] - '0'; in path_to_channel()
286 if (elem[i] != '\0') { in path_to_channel()
379 int i; in devwalk() local
390 for (i = 0; ; i++) { in devwalk()
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| /rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.h | 39 #define PLL_CONS(id, i) (0x020 * (id) + ((i) * 4)) argument
40 #define CRU_CLKSEL_CON(i) (0x100 + ((i) * 4)) argument
42 #define CRU_CLKGATE_CON(i) (0x200 + ((i) * 4)) argument
62 #define CRU_CONS_GATEID(i) (16 * (i)) argument
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/ |
| H A D | rk3399_gpio.c | 305 unsigned int i; in plat_rockchip_save_gpio() local
324 for (i = 2; i < 5; i++) { in plat_rockchip_save_gpio()
325 uint32_t base = port_info[i].port_base; in plat_rockchip_save_gpio()
327 store_gpio[i - 2] = (struct gpio_save) { in plat_rockchip_save_gpio()
346 for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++) in plat_rockchip_save_gpio()
347 store_grf_gpio[i] = in plat_rockchip_save_gpio()
348 mmio_read_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4); in plat_rockchip_save_gpio()
353 int i; in plat_rockchip_restore_gpio() local
356 for (i = 0; i < ARRAY_SIZE(store_grf_gpio); i++) in plat_rockchip_restore_gpio()
357 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4, in plat_rockchip_restore_gpio()
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/devapc/ |
| H A D | devapc.c | 2467 int d, i; in dump_infra_ao_apc() local
2471 for (i = 0; i <= reg_num; i++) { in dump_infra_ao_apc()
2473 d, i, devapc_readl( in dump_infra_ao_apc()
2475 d * 0x40 + i * 4) in dump_infra_ao_apc()
2482 for (i = 0; i <= reg_num; i++) { in dump_infra_ao_apc()
2484 d, i, devapc_readl( in dump_infra_ao_apc()
2486 d * 0x40 + i * 4) in dump_infra_ao_apc()
2493 for (i = 0; i <= reg_num; i++) { in dump_infra_ao_apc()
2495 d, i, devapc_readl( in dump_infra_ao_apc()
2497 d * 0x40 + i * 4) in dump_infra_ao_apc()
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| /rk3399_ARM-atf/plat/imx/common/ |
| H A D | imx_csu.c | 14 int i; in imx_csu_init() local
17 for (i = 0; i < MXC_MAX_CSU_REGS; i++, csl_reg++) in imx_csu_init()
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| /rk3399_ARM-atf/plat/imx/imx8m/ |
| H A D | gpc_common.c | 206 for (int i = 0; i < IRQ_IMR_NUM; i++) { in imx_set_sys_wakeup() local
209 irq_mask = ~gicd_read_isenabler(gicd_base, 32 * (i + 1)); in imx_set_sys_wakeup()
213 mmio_write_32(IMX_GPC_BASE + gpc_imr_offset[last_core] + i * 4, in imx_set_sys_wakeup()
278 unsigned int i; in imx_anamix_override() local
284 for (i = 0U; i < MAX_PLL_NUM; i++) { in imx_anamix_override()
286 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); in imx_anamix_override()
287 mmio_setbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); in imx_anamix_override()
289 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, PLL_BYPASS); in imx_anamix_override()
290 mmio_clrbits_32(IMX_ANAMIX_BASE + pll[i].reg, pll[i].override_mask); in imx_anamix_override()
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/ |
| H A D | hikey960_bl2_setup.c | 53 int i; in plat_hikey960_bl2_handle_scp_bl2() local
67 for (i = 0; i < 64; i += 4) in plat_hikey960_bl2_handle_scp_bl2()
69 buf[i], buf[i+1], buf[i+2], buf[i+3]); in plat_hikey960_bl2_handle_scp_bl2()
75 for (i = 0; i < 64; i += 4) in plat_hikey960_bl2_handle_scp_bl2()
77 buf[i], buf[i+1], buf[i+2], buf[i+3]); in plat_hikey960_bl2_handle_scp_bl2()
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| /rk3399_ARM-atf/plat/marvell/armada/common/ |
| H A D | marvell_topology.c | 20 int i; in plat_get_power_domain_tree_desc() local
31 for (i = 0; i < PLAT_MARVELL_CLUSTER_COUNT; i++) in plat_get_power_domain_tree_desc()
32 marvell_power_domain_tree_desc[i + 1] = in plat_get_power_domain_tree_desc()
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| /rk3399_ARM-atf/plat/brcm/board/stingray/driver/ext_sram_init/ |
| H A D | ext_sram_init.c | 19 unsigned int i; in brcm_stingray_pnor_pinmux_init() local
79 for (i = 0; i < 0x40; i += 0x4) { in brcm_stingray_pnor_pinmux_init()
80 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x308 + i), in brcm_stingray_pnor_pinmux_init()
116 for (i = 0; i < 0x40; i += 0x4) { in brcm_stingray_pnor_pinmux_init()
117 mmio_clrsetbits_32((uintptr_t)(HSLS_IOPAD_BASE + 0x360 + i), in brcm_stingray_pnor_pinmux_init()
183 unsigned int off, i; in brcm_stingray_pnor_sram_init() local
263 i = (off / SRAM_CHECKS_GRANUL) % SRAM_CHECKS_CNT; in brcm_stingray_pnor_sram_init()
264 val = sram_checks[i]; in brcm_stingray_pnor_sram_init()
272 i = (off / SRAM_CHECKS_GRANUL) % SRAM_CHECKS_CNT; in brcm_stingray_pnor_sram_init()
277 if (val == sram_checks[i]) in brcm_stingray_pnor_sram_init()
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| /rk3399_ARM-atf/drivers/ti/ipc/ |
| H A D | sec_proxy.c | 200 int num_words, trail_bytes, i, ret; in ti_sci_transport_send() local
220 for (i = 0; i < num_words; i++) { in ti_sci_transport_send()
221 mmio_write_32(spt->data + data_reg, ((uint32_t *)msg->buf)[i]); in ti_sci_transport_send()
230 i = msg->len - trail_bytes; in ti_sci_transport_send()
233 data_trail |= msg->buf[i++]; in ti_sci_transport_send()
267 int num_words, trail_bytes, i, ret; in ti_sci_transport_recv() local
279 for (i = 0; i < num_words; i++) { in ti_sci_transport_recv()
280 ((uint32_t *)msg->buf)[i] = mmio_read_32(spt->data + data_reg); in ti_sci_transport_recv()
290 i = msg->len - trail_bytes; in ti_sci_transport_recv()
292 msg->buf[i++] = data_trail & 0xff; in ti_sci_transport_recv()
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| /rk3399_ARM-atf/plat/xilinx/common/ |
| H A D | plat_startup.c | 220 for (size_t i = 0; i < HandoffParams->num_entries; i++) { in xbl_handover() local
225 VERBOSE("BL31: %zd: entry:0x%" PRIx64 ", flags:0x%" PRIx64 "\n", i, in xbl_handover()
226 HandoffParams->partition[i].entry_point, in xbl_handover()
227 HandoffParams->partition[i].flags); in xbl_handover()
232 target_cluster = get_xbl_cluster(&HandoffParams->partition[i]); in xbl_handover()
240 target_cpu = get_xbl_cpu(&HandoffParams->partition[i]); in xbl_handover()
246 target_el = get_xbl_el(&HandoffParams->partition[i]); in xbl_handover()
254 target_secure = get_xbl_ss(&HandoffParams->partition[i]); in xbl_handover()
262 target_estate = get_xbl_estate(&HandoffParams->partition[i]); in xbl_handover()
263 target_endianness = get_xbl_endian(&HandoffParams->partition[i]); in xbl_handover()
[all …]
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/aarch64/ |
| H A D | zynqmp_common.c | 239 size_t i, j, len; in zynqmp_get_silicon_idcode_name() local
251 for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) { in zynqmp_get_silicon_idcode_name()
252 if ((zynqmp_devices[i].id == id) && in zynqmp_get_silicon_idcode_name()
253 (zynqmp_devices[i].ver == (ver & ZYNQMP_CSU_VERSION_MASK))) { in zynqmp_get_silicon_idcode_name()
258 if (i >= ARRAY_SIZE(zynqmp_devices)) { in zynqmp_get_silicon_idcode_name()
269 if (!zynqmp_devices[i].evexists) { in zynqmp_get_silicon_idcode_name()
270 return zynqmp_devices[i].name; in zynqmp_get_silicon_idcode_name()
274 return zynqmp_devices[i].name; in zynqmp_get_silicon_idcode_name()
277 len = strlen(zynqmp_devices[i].name) - 2U; in zynqmp_get_silicon_idcode_name()
279 zynqmp_devices[i].name[len] = name[j]; in zynqmp_get_silicon_idcode_name()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/emi_mpu/ |
| H A D | emi_mpu.c | 77 int i; in emi_mpu_set_protection() local
87 for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) { in emi_mpu_set_protection()
89 (i << 24); in emi_mpu_set_protection()
90 _emi_mpu_set_protection(start, end, region_info->apc[i]); in emi_mpu_set_protection()
100 int region, i; in dump_emi_mpu_regions() local
104 for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i) in dump_emi_mpu_regions()
105 apc[i] = mmio_read_32(EMI_MPU_APC(region, i)); in dump_emi_mpu_regions()
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| /rk3399_ARM-atf/services/std_svc/rmmd/ |
| H A D | rmmd_attest.c | 39 unsigned int i; in print_challenge() local
41 for (i = 0U; i < hash_size; ++i) { in print_challenge()
42 hash_text[(i & (bytes_per_line - 1)) * DIGITS_PER_BYTE] = in print_challenge()
43 hex_chars[hash[i] >> 4]; in print_challenge()
44 hash_text[(i & (bytes_per_line - 1)) * DIGITS_PER_BYTE + 1] = in print_challenge()
45 hex_chars[hash[i] & 0x0f]; in print_challenge()
46 if (((i + 1) & (bytes_per_line - 1)) == 0U) { in print_challenge()
49 (i >> BYTES_PER_LINE_BASE) + 1, hash_text); in print_challenge()
53 leftover = (size_t)i & (bytes_per_line - 1); in print_challenge()
57 VERBOSE("hash part %u = %s\n", (i >> BYTES_PER_LINE_BASE) + 1, in print_challenge()
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| /rk3399_ARM-atf/drivers/renesas/rzg/qos/ |
| H A D | qos_init.c | 63 uint32_t i; in rzg_qos_init() local
67 for (i = 0U; i < DRAM_CH_CNT; i++) { in rzg_qos_init()
68 if ((qos_init_ddr_phyvalid & (1U << i))) { in rzg_qos_init()
252 unsigned int i; in rzg_qos_dbsc_setting() local
259 for (i = 0; i < qos_size; i++) { in rzg_qos_dbsc_setting()
260 mmio_write_32(qos[i].reg, qos[i].val); in rzg_qos_dbsc_setting()
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| /rk3399_ARM-atf/plat/xilinx/zynqmp/ |
| H A D | bl31_zynqmp_setup.c | 163 uint32_t i; in request_intr_type_el3() local
171 for (i = 0; i < index; i++) { in request_intr_type_el3()
172 if (id == type_el3_interrupt_table[i].id) { in request_intr_type_el3()
189 uint32_t i; in rdo_el3_interrupt_handler() local
194 for (i = 0; i < MAX_INTR_EL3; i++) { in rdo_el3_interrupt_handler()
195 if (intr_id == type_el3_interrupt_table[i].id) { in rdo_el3_interrupt_handler()
196 handler = type_el3_interrupt_table[i].handler; in rdo_el3_interrupt_handler()
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| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hisi_mcu.c | 159 unsigned int i; in hisi_mcu_load_image() local
170 for (i = 0; i < head->secs_num; i++) { in hisi_mcu_load_image()
175 if (is_binary_section_invalid(&head->secs[i], head)) { in hisi_mcu_load_image()
181 if (head->secs[i].load_attr != MCU_IMAGE_SEC_LOAD_STATIC) in hisi_mcu_load_image()
185 src = (int *)(intptr_t)(buf + head->secs[i].src_offset); in hisi_mcu_load_image()
186 dst = (int *)(intptr_t)mcu2ap_addr(head->secs[i].dst_offset); in hisi_mcu_load_image()
188 memcpy((void *)dst, (void *)src, head->secs[i].size); in hisi_mcu_load_image()
190 INFO("%s: mcu sections %d:\n", __func__, i); in hisi_mcu_load_image()
195 INFO("%s: size = %d\n", __func__, head->secs[i].size); in hisi_mcu_load_image()
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| H A D | hikey_security.c | 75 uint32_t i = 0; in sec_protect() local
90 for (i = 0; i < PORTNUM_MAX; i++) { in sec_protect()
91 rgn_map = get_rgn_map_reg(MDDRC_SECURITY_BASE, region, i); in sec_protect()
92 rgn_attr = get_rgn_attr_reg(MDDRC_SECURITY_BASE, region, i); in sec_protect()
95 rgn_attr->sp = (i == 3) ? 0xC : 0x0; in sec_protect()
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| /rk3399_ARM-atf/docs/resources/diagrams/plantuml/ |
| H A D | fip-secure-partitions.puml | 79 <i>header</i>
89 <i>header</i>
103 <i>header</i>
109 <i>signature</I>
115 <i>header</i>
121 <i>signature</I>
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| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/emi_mpu/ |
| H A D | emi_mpu.c | 121 int i; in dump_emi_mpu_regions() local
123 for (i = 0; i < 8; ++i) { in dump_emi_mpu_regions()
124 apc = mmio_read_32(apc_addr + i * 4); in dump_emi_mpu_regions()
125 sa = mmio_read_32(sa_addr + i * 4); in dump_emi_mpu_regions()
126 ea = mmio_read_32(ea_addr + i * 4); in dump_emi_mpu_regions()
127 WARN("region %d:\n", i); in dump_emi_mpu_regions()
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| /rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/ |
| H A D | soc.h | 42 #define CRU_CLKSELS_CON(i) (CRU_CLKSEL_CON + ((i) * 4)) argument
46 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4)) argument
53 #define CRU_CONS_GATEID(i) (16 * (i)) argument
65 #define PLL_CONS(id, i) ((id) * 0x10 + ((i) * 4)) argument
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| /rk3399_ARM-atf/plat/arm/board/arm_fpga/ |
| H A D | fpga_topology.c | 20 unsigned int i; in plat_get_power_domain_tree_desc() local
44 for (i = 0U; i < FPGA_MAX_CLUSTER_COUNT; i++) { in plat_get_power_domain_tree_desc()
45 fpga_power_domain_tree_desc[2 + i] = in plat_get_power_domain_tree_desc()
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| /rk3399_ARM-atf/plat/imx/imx8ulp/scmi/ |
| H A D | scmi.c | 64 size_t i; in imx8ulp_init_scmi_server() local
66 for (i = 0U; i < ARRAY_SIZE(scmi_channel); i++) { in imx8ulp_init_scmi_server()
67 scmi_smt_init_agent_channel(&scmi_channel[i]); in imx8ulp_init_scmi_server()
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| /rk3399_ARM-atf/drivers/auth/mbedtls/ |
| H A D | mbedtls_psa_crypto.c | 114 for (int i = 0; i < MAX_CACHED_KEYS; i++) { in destroy_key_ids() local
115 if (key_cache[i].valid) { in destroy_key_ids()
116 psa_destroy_key(key_cache[i].key_id); in destroy_key_ids()
125 for (int i = 0; i < MAX_CACHED_KEYS; i++) { in get_cached_psa_key_info() local
126 if (key_cache[i].valid && in get_cached_psa_key_info()
127 (strlen(key_cache[i].pk_oid) == strlen(pk_oid)) && in get_cached_psa_key_info()
128 (strncmp(key_cache[i].pk_oid, pk_oid, strlen(pk_oid)) == 0)) { in get_cached_psa_key_info()
129 *key_id = key_cache[i].key_id; in get_cached_psa_key_info()
130 *psa_alg = key_cache[i].psa_alg; in get_cached_psa_key_info()
131 *psa_key_attr = key_cache[i].psa_key_attr; in get_cached_psa_key_info()
[all …]
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