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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_px30.c | fda8d8733197b2e36a551d20f88252d078b1660a Tue Jan 15 07:43:23 UTC 2019 Elaine Zhang <zhangqing@rock-chips.com> clk: rockchip: px30: modify the dclk divider to even
When DCLK use CPLL alone, the DCLK timing is critical value.
The odd-divider spacing ratio is not 50%,
it will affect the setup time of the display.
Therefore, it is suggested that we use even-divider
to make the spacing ratio is 50%.
Change-Id: I07c0fd57dd1f27984f8186f1d7c2f96df2ea10a3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
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