Searched hist:f9c6301d743405bd91b9a1fe433ce14fa60a830f (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x2.S | f9c6301d743405bd91b9a1fe433ce14fa60a830f Thu Dec 22 20:19:59 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X2 erratum 2282622
Cortex-X2 erratum 2282622 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to set
CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43956aa4898a8608eedc5d0dd1471172c641a0c6
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| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | f9c6301d743405bd91b9a1fe433ce14fa60a830f Thu Dec 22 20:19:59 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X2 erratum 2282622
Cortex-X2 erratum 2282622 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to set
CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43956aa4898a8608eedc5d0dd1471172c641a0c6
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | f9c6301d743405bd91b9a1fe433ce14fa60a830f Thu Dec 22 20:19:59 UTC 2022 Bipin Ravi <bipin.ravi@arm.com> fix(cpus): workaround for Cortex-X2 erratum 2282622
Cortex-X2 erratum 2282622 is a Cat B erratum that applies to
all revisions <=r2p1 and is still open. The workaround is to set
CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to behave like
PLD/PRFM LD and not cause invalidations to other PE caches.
SDEN documentation:
https://developer.arm.com/documentation/SDEN1775100/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: I43956aa4898a8608eedc5d0dd1471172c641a0c6
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