Searched hist:f828efe258e148b2707249a65b2e31ab9718c4a6 (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_x3.S | f828efe258e148b2707249a65b2e31ab9718c4a6 Mon Jun 30 21:22:46 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X3 erratum 3692984
Cortex-X3 erratum 3692984 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2 and is still open.
The erratum can be avoided by disabling the
affected prefetcher setting CPUACTLR6_EL1[41].
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I054b47d33fd1ff7bde3ae12e8ee3d99e9203965f
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| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | f828efe258e148b2707249a65b2e31ab9718c4a6 Mon Jun 30 21:22:46 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X3 erratum 3692984
Cortex-X3 erratum 3692984 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2 and is still open.
The erratum can be avoided by disabling the
affected prefetcher setting CPUACTLR6_EL1[41].
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I054b47d33fd1ff7bde3ae12e8ee3d99e9203965f
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| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | f828efe258e148b2707249a65b2e31ab9718c4a6 Mon Jun 30 21:22:46 UTC 2025 Arvind Ram Prakash <arvind.ramprakash@arm.com> fix(cpus): workaround for Cortex-X3 erratum 3692984
Cortex-X3 erratum 3692984 is a Cat B erratum that applies to
r0p0, r1p0, r1p1 and r1p2 and is still open.
The erratum can be avoided by disabling the
affected prefetcher setting CPUACTLR6_EL1[41].
SDEN Documentation:
https://developer.arm.com/documentation/SDEN-2055130/latest/
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I054b47d33fd1ff7bde3ae12e8ee3d99e9203965f
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