Searched hist:f7e7ea1fa39f6fe9601c84c19f72029c4d2c257c (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/plat/imx/common/ |
| H A D | imx9_sm_sema.c | f7e7ea1fa39f6fe9601c84c19f72029c4d2c257c Thu Aug 22 22:34:08 UTC 2024 Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> feat(imx95): implement a semaphore for GIC quiescing
As there is no way to reset the GIC on iMX95, SM(System Controller)
needs to quiesce the GIC using the GIC waker. But AP can also be
touching GIC waker register during entry/exit from low power modes.
Add a semaphore to provide a critical section for GIC waker. The last
two words in the TF-A MU 1K SRAM space is used to hold the semaphore
(follow the Peterson'salgorithm for mutual exclusion).
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic5d696ac83668e72d9c3204d7ec047ac9f751e94
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| H A D | plat_imx8_gic.c | f7e7ea1fa39f6fe9601c84c19f72029c4d2c257c Thu Aug 22 22:34:08 UTC 2024 Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> feat(imx95): implement a semaphore for GIC quiescing
As there is no way to reset the GIC on iMX95, SM(System Controller)
needs to quiesce the GIC using the GIC waker. But AP can also be
touching GIC waker register during entry/exit from low power modes.
Add a semaphore to provide a critical section for GIC waker. The last
two words in the TF-A MU 1K SRAM space is used to hold the semaphore
(follow the Peterson'salgorithm for mutual exclusion).
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic5d696ac83668e72d9c3204d7ec047ac9f751e94
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| /rk3399_ARM-atf/plat/imx/imx9/imx95/include/ |
| H A D | platform_def.h | f7e7ea1fa39f6fe9601c84c19f72029c4d2c257c Thu Aug 22 22:34:08 UTC 2024 Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> feat(imx95): implement a semaphore for GIC quiescing
As there is no way to reset the GIC on iMX95, SM(System Controller)
needs to quiesce the GIC using the GIC waker. But AP can also be
touching GIC waker register during entry/exit from low power modes.
Add a semaphore to provide a critical section for GIC waker. The last
two words in the TF-A MU 1K SRAM space is used to hold the semaphore
(follow the Peterson'salgorithm for mutual exclusion).
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic5d696ac83668e72d9c3204d7ec047ac9f751e94
|
| /rk3399_ARM-atf/plat/imx/imx9/imx95/ |
| H A D | platform.mk | f7e7ea1fa39f6fe9601c84c19f72029c4d2c257c Thu Aug 22 22:34:08 UTC 2024 Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> feat(imx95): implement a semaphore for GIC quiescing
As there is no way to reset the GIC on iMX95, SM(System Controller)
needs to quiesce the GIC using the GIC waker. But AP can also be
touching GIC waker register during entry/exit from low power modes.
Add a semaphore to provide a critical section for GIC waker. The last
two words in the TF-A MU 1K SRAM space is used to hold the semaphore
(follow the Peterson'salgorithm for mutual exclusion).
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic5d696ac83668e72d9c3204d7ec047ac9f751e94
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