| #
480e8dd9 |
| 25-Aug-2025 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "Add-i.MX94/95-suport" into integration
* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee s
Merge changes from topic "Add-i.MX94/95-suport" into integration
* changes:
docs(maintainers): add i.MX9 to maintained paths
feat(imx94): add initial support for imx94
feat(imx95): add optee support
feat(imx95): support trusty os
feat(imx95): implement a semaphore for GIC quiescing
feat(imx95): add initial support for i.MX95
feat(imx9): add necessary ele api call support
feat(imx9): add imx9 common code base
refactor(imx): drop the __dead2 attribute
fix(imx): add static attribute for platform specific gic struct
feat(gic): change gic_cpuif_enable/disable to weak
feat(scmi): add i.MX9 SCMI vendor CPU protocol
feat(scmi): add base protocol agent API
feat(scmi): update version to 3.0
build(changelog): update for imx94/95 support
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| #
f7e7ea1f |
| 22-Aug-2024 |
Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> |
feat(imx95): implement a semaphore for GIC quiescing
As there is no way to reset the GIC on iMX95, SM(System Controller)
needs to quiesce the GIC using the GIC waker. But AP can also be
touching GIC
feat(imx95): implement a semaphore for GIC quiescing
As there is no way to reset the GIC on iMX95, SM(System Controller)
needs to quiesce the GIC using the GIC waker. But AP can also be
touching GIC waker register during entry/exit from low power modes.
Add a semaphore to provide a critical section for GIC waker. The last
two words in the TF-A MU 1K SRAM space is used to hold the semaphore
(follow the Peterson'salgorithm for mutual exclusion).
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: Ic5d696ac83668e72d9c3204d7ec047ac9f751e94
show more ...
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