Searched hist:f6b96ff665844291a76de139bfbaa75fc0c7d917 (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | immap_lsch3.h | f6b96ff665844291a76de139bfbaa75fc0c7d917 Thu Nov 17 06:59:52 UTC 2016 Priyanka Jain <priyanka.jain@nxp.com> armv8: lsch3: Use SVR based timer base address detection
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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| H A D | soc.h | f6b96ff665844291a76de139bfbaa75fc0c7d917 Thu Nov 17 06:59:52 UTC 2016 Priyanka Jain <priyanka.jain@nxp.com> armv8: lsch3: Use SVR based timer base address detection
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | cpu.c | f6b96ff665844291a76de139bfbaa75fc0c7d917 Thu Nov 17 06:59:52 UTC 2016 Priyanka Jain <priyanka.jain@nxp.com> armv8: lsch3: Use SVR based timer base address detection
Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.
Use SVR based timer base address detection to avoid compile time #ifdef.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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