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| /rk3399_rockchip-uboot/drivers/clk/rockchip/ |
| H A D | clk_px30.c | f5b1a4f280dfab437fa37422a2537e0eef860011 Thu Mar 17 02:50:31 UTC 2022 Jianqun Xu <jay.xu@rock-chips.com> clk: rockchip: px30 set i2s1 mclk out rate to 11289600 Hz
The px30 i2s1 mclk default to source from gpll, it may outputs 100 MHz
when the gpll rate up to 1200MHz. Some slave codec may fail to work at
the high frequency.
This patch will set the i2s1 mclk source from xin_osc_half before gpll
rate up, and then set to 11289600 Hz after gpll rate up.
Change-Id: I2a7641ed7c0db794e50aaacbbc6bb361a8b5db72
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
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