Searched hist:ec9aa1a4114f50f8091cb7088cfa9f6c0cc1c51b (Results 1 – 2 of 2) sorted by relevance
| /optee_os/core/drivers/ |
| H A D | stm32_hsem.c | ec9aa1a4114f50f8091cb7088cfa9f6c0cc1c51b Wed Mar 27 15:33:55 UTC 2024 Gatien Chevallier <gatien.chevallier@foss.st.com> drivers: add RIF support driver for HSEM
This driver implements RIF configuration for HSEM, which is a RIF
aware IP. It means that the HSEM driver is in charge of configuring its
own RIF restrictions and that the HSEM has dedicated RIF configuration
registers.
HSEM has two types of CID filtering registers.
-For processor filtering : HSEM_CnCIDCFGR
When CFEN is enabled: processor[n] CID filtering enabled for HSEM_(S)CnIER,
HSEM_(S)CnICR, HSEM_(S)CnISR, and HSEM_(S)CnMISR registers and for allowed
list filter usage in HSEM_GpCIDCFGR.SEM_WLIST_Cn. The CID is put in the
CID bitfield.
-For semaphore group filtering : HSEM_GpCIDCFGR
Used to apply CID filtering over a group of semaphore. The same policy
applies to all semaphores present in the group. This register handles
what are the processor's CID who are white-listed for the group in the
SEM_WLIST_C bitfield.
Therefore, both these registers are interconnected.
Security and privilege configuration granularity expands to each individual
semaphore.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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| H A D | sub.mk | ec9aa1a4114f50f8091cb7088cfa9f6c0cc1c51b Wed Mar 27 15:33:55 UTC 2024 Gatien Chevallier <gatien.chevallier@foss.st.com> drivers: add RIF support driver for HSEM
This driver implements RIF configuration for HSEM, which is a RIF
aware IP. It means that the HSEM driver is in charge of configuring its
own RIF restrictions and that the HSEM has dedicated RIF configuration
registers.
HSEM has two types of CID filtering registers.
-For processor filtering : HSEM_CnCIDCFGR
When CFEN is enabled: processor[n] CID filtering enabled for HSEM_(S)CnIER,
HSEM_(S)CnICR, HSEM_(S)CnISR, and HSEM_(S)CnMISR registers and for allowed
list filter usage in HSEM_GpCIDCFGR.SEM_WLIST_Cn. The CID is put in the
CID bitfield.
-For semaphore group filtering : HSEM_GpCIDCFGR
Used to apply CID filtering over a group of semaphore. The same policy
applies to all semaphores present in the group. This register handles
what are the processor's CID who are white-listed for the group in the
SEM_WLIST_C bitfield.
Therefore, both these registers are interconnected.
Security and privilege configuration granularity expands to each individual
semaphore.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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