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| /rk3399_rockchip-uboot/include/dt-bindings/phy/ |
| H A D | phy-snps-pcie3.h | eb6fc1c20bb3c2177dc69cd048b7996242b0f6d3 Sun Nov 21 04:28:58 UTC 2021 Jon Lin <jon.lin@rock-chips.com> phy: phy-rockchip-snps-pcie3: Add pcie3_phymode setting
rk3588 pcie3 phy has a pcie3_phymode to decide how to use the four
lanes, add support in dts so that we can customize in dts.
The phy has two port and each port has two lane:
pcie30_phy_mode[2:0]
2: aggregation
1: bifurcation for port 1
0: bifurcation for port 0
Change-Id: I0bdf75b8df7c927f8a59ddb7ec3739b3c9f33a49
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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