Searched hist:eb5394120643922626f18e5fe7b0b3dc0ed43b9a (Results 1 – 7 of 7) sorted by relevance
| /rk3399_rockchip-uboot/arch/powerpc/include/asm/ |
| H A D | mp.h | eb5394120643922626f18e5fe7b0b3dc0ed43b9a Mon Oct 08 07:44:25 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| H A D | config_mpc85xx.h | eb5394120643922626f18e5fe7b0b3dc0ed43b9a Mon Oct 08 07:44:25 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc86xx/ |
| H A D | mp.c | eb5394120643922626f18e5fe7b0b3dc0ed43b9a Mon Oct 08 07:44:25 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| H A D | fdt.c | eb5394120643922626f18e5fe7b0b3dc0ed43b9a Mon Oct 08 07:44:25 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/ |
| H A D | mp.c | eb5394120643922626f18e5fe7b0b3dc0ed43b9a Mon Oct 08 07:44:25 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| H A D | fdt.c | eb5394120643922626f18e5fe7b0b3dc0ed43b9a Mon Oct 08 07:44:25 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| H A D | cmd_errata.c | eb5394120643922626f18e5fe7b0b3dc0ed43b9a Mon Oct 08 07:44:25 UTC 2012 York Sun <yorksun@freescale.com> powerpc/mpc85xx: software workaround for DDR erratum A-004468
Boot space translation utilizes the pre-translation address to select
the DDR controller target. However, the post-translation address will be
presented to the selected DDR controller. It is possible that the pre-
translation address selects one DDR controller but the post-translation
address exists in a different DDR controller when using certain DDR
controller interleaving modes. The device may fail to boot under these
circumstances. Note that a DDR MSE error will not be detected since DDR
controller bounds registers are programmed to be the same when configured
for DDR controller interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
|