Searched hist:ea88493655a82b9f363951cf6b604ff21cd711f0 (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch64/ |
| H A D | cortex_a510.S | ea88493655a82b9f363951cf6b604ff21cd711f0 Fri Aug 29 23:44:16 UTC 2025 John Powell <john.powell@arm.com> fix(cpus): workaround for Cortex-A510 erratum 3704847
Cortex-A510 erratum 3704847 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.
The workaround is to set bit 9 in CPUACTLR_EL1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/
Change-Id: I2c7c8da9c66471115b5bf8fb5c87d4de46ca265c
Signed-off-by: John Powell <john.powell@arm.com>
|
| /rk3399_ARM-atf/docs/design/ |
| H A D | cpu-specific-build-macros.rst | ea88493655a82b9f363951cf6b604ff21cd711f0 Fri Aug 29 23:44:16 UTC 2025 John Powell <john.powell@arm.com> fix(cpus): workaround for Cortex-A510 erratum 3704847
Cortex-A510 erratum 3704847 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.
The workaround is to set bit 9 in CPUACTLR_EL1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/
Change-Id: I2c7c8da9c66471115b5bf8fb5c87d4de46ca265c
Signed-off-by: John Powell <john.powell@arm.com>
|
| /rk3399_ARM-atf/lib/cpus/ |
| H A D | cpu-ops.mk | ea88493655a82b9f363951cf6b604ff21cd711f0 Fri Aug 29 23:44:16 UTC 2025 John Powell <john.powell@arm.com> fix(cpus): workaround for Cortex-A510 erratum 3704847
Cortex-A510 erratum 3704847 is a Cat B erratum that applies to
revisions r0p0, r0p1, r0p2, r0p3, r1p0, r1p1, r1p2 and r1p3, and
is still open.
The workaround is to set bit 9 in CPUACTLR_EL1.
SDEN documentation:
https://developer.arm.com/documentation/SDEN-1873361/latest/
Change-Id: I2c7c8da9c66471115b5bf8fb5c87d4de46ca265c
Signed-off-by: John Powell <john.powell@arm.com>
|