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| /optee_os/core/drivers/clk/sam/ |
| H A D | clk-sam9x60-pll.c | e83d19065432ec321639a2d4c4e69e06848225f2 Thu Jan 09 05:36:29 UTC 2025 Tony Han <tony.han@microchip.com> drivers: clk: sam: fix operation on wrong PMC_PLL_CTRLx registers
When writing/reading a PLL control register (PMC_PLL_CTRLx), the ID in
PMC_PLL_UPDT specifies which PLL fields are written/read. Set correct ID
to PMC_PLL_UPDT to avoid operating on wrong PMC_PLL_CTRLx.
Fixes: 4318c69fa77d ("drivers: clk: sam: add PLL clock driver for sama7g5")
Signed-off-by: Tony Han <tony.han@microchip.com>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>
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