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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | stm32mp1_clk.c | dd98aec87ca83054c9bc7502d018e46b02536eb1 Tue Jun 04 13:55:37 UTC 2019 Yann Gautier <yann.gautier@st.com> clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the CSG option, the driver needs to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator.
This bit should not be cleared when starting the PLL.
Change-Id: Ie5c720ff03655f27a7e7e9e7ccf8295dd046112f
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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