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| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip_vop2.c | dd0d7bfe1a5fa4ca21cd2652443732f662c69d57 Tue Apr 01 07:47:38 UTC 2025 Damon Ding <damon.ding@rock-chips.com> video/drm: vop2: calculate dclk divisions in Hz instead of KHz for RK3588
If MIPI0 is enabled and the &drm_display_mode.crtc_clock is 74250
in Khz that is equal with pixel clock rate, dclk_core_rate will be
18562 in Khz, which is a quarter of pixel clock rate.
After the vop2_calc_dclk(), the final dclk rate will be four times
dclk_out_rate, which is the same as dclk_core_rate unless DSC mode
is enabled or the dual channel mode is configrated, is 74248 in KHz.
Then the dclk rate will be set to 74248000Hz unexpectly.
In conclusion, it will be more accurate to calculate dclk divisions
in Hz instead of KHz as the Kernel.
Change-Id: Ib31f5b18c739ca4044a3278cd940367805b9d4ee
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
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