"dbf89912a42ce800d4e5f12bf4c2643a4e3d3773" (history) in projects: rk3399_rockchip-uboot

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/rk3399_rockchip-uboot/drivers/phy/
H A D	phy-rockchip-naneng-combphy.c	`dbf89912a42ce800d4e5f12bf4c2643a4e3d3773 Thu Mar 18 07:20:03 UTC 2021 Ren Jianing <jianing.ren@rock-chips.com> phy: rockchip: fix reset and clk error for naneng combphy The combphy has two resets. If we get reset by index 0, we will get apb-reset rather than phy-reset. Besides, the delault ref-clk of combphy is 25MHz. Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com> Change-Id: I57349b6a28a6e5c15f86f24030bbf85d50be94e8`