Home
last modified time | relevance | path

Searched hist:db9b4c53f22e3b5cbec3fca34a69650ad2d1e0a6 (Results 1 – 1 of 1) sorted by relevance

/rk3399_rockchip-uboot/common/spl/
H A Dspl.cdb9b4c53f22e3b5cbec3fca34a69650ad2d1e0a6 Tue Apr 28 08:02:44 UTC 2020 Jason Zhu <jason.zhu@rock-chips.com> common: spl: change TLB memory base align to SZ_16K

According to armv7 spec, translation table base 0 address is align to
2^(14-n). The n is set by TTBCR and is set to zero in uboot.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I3d4c3f7165d3ef27bcc51d90471830f5e6dccae5