Searched hist:dac93f83704b40b68ba21a704af7b37fa085bf64 (Results 1 – 3 of 3) sorted by relevance
| /rk3399_rockchip-uboot/drivers/video/drm/ |
| H A D | rockchip_vop.h | dac93f83704b40b68ba21a704af7b37fa085bf64 Wed Aug 18 08:29:41 UTC 2021 Chris Zhong <zyw@rock-chips.com> drm/rockchip: vop: correct the dclk_inv
The property pixelclk-active=1 in dts means dclk polarity is positive
edge, and set 0 to GRF or VOP register: lcdc_dclk_inv_sel. This bit
is reversed in uboot, this patch corrects it.
In addition, the configuration of RV1126 has been added in this patch.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Change-Id: I93af7e052fb18782a81e9c9b762a57411ef9283f
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| H A D | rockchip_vop_reg.c | dac93f83704b40b68ba21a704af7b37fa085bf64 Wed Aug 18 08:29:41 UTC 2021 Chris Zhong <zyw@rock-chips.com> drm/rockchip: vop: correct the dclk_inv
The property pixelclk-active=1 in dts means dclk polarity is positive
edge, and set 0 to GRF or VOP register: lcdc_dclk_inv_sel. This bit
is reversed in uboot, this patch corrects it.
In addition, the configuration of RV1126 has been added in this patch.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Change-Id: I93af7e052fb18782a81e9c9b762a57411ef9283f
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| H A D | rockchip_vop.c | dac93f83704b40b68ba21a704af7b37fa085bf64 Wed Aug 18 08:29:41 UTC 2021 Chris Zhong <zyw@rock-chips.com> drm/rockchip: vop: correct the dclk_inv
The property pixelclk-active=1 in dts means dclk polarity is positive
edge, and set 0 to GRF or VOP register: lcdc_dclk_inv_sel. This bit
is reversed in uboot, this patch corrects it.
In addition, the configuration of RV1126 has been added in this patch.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Change-Id: I93af7e052fb18782a81e9c9b762a57411ef9283f
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